summaryrefslogtreecommitdiff
path: root/jtag_uart.c
blob: 5f3e9d8a3e4132bd526ebdee283334415743e307 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
/*
 * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
 * Copyright (C) 2010 chysun2000@gmail.com
 *
 * This file is part of nios2sim-ng.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <stdio.h>
#include <stdlib.h>

#include "nios2sim-ng.h"
#include "device.h"
#include "jtag_uart.h"

#define JTAG_UART_CLK_COUNT_INIT	500

#define jtag_uart_printf(fmt, args...)	fprintf(stdout, fmt, ##args)

struct jtag_uart_fifo {
	uint8_t data;
	bool has_data;
};

struct jtag_uart {
	struct io_register regs[JTAG_UART_REG_COUNT];
	struct jtag_uart_fifo tx_fifo;
	unsigned int clk_count;
};

static const uint32_t jtag_uart_valid_mask[JTAG_UART_REG_COUNT] = {
	0xFFFF80FF,	/* data */
	0xFFFF0703,	/* control */
};

static const uint32_t jtag_uart_readonly_mask[JTAG_UART_REG_COUNT] = {
	0xFFFF8000,	/* data */
	0xFFFF0300,	/* control */
};

static int jtag_uart_init(struct device *dev)
{
	struct jtag_uart *ju;
	struct io_register *regs;
	unsigned int i;

	ju = malloc(sizeof(struct jtag_uart));
	if (unlikely(ju == NULL))
		return -1;

	/* Initialite registers */
	regs = ju->regs;
	for (i = 0; i < JTAG_UART_REG_COUNT; i++) {
		io_register_init(&regs[i],
				 JTAG_UART_BASE + REG_TO_OFF(i),
				 jtag_uart_valid_mask[i],
				 jtag_uart_readonly_mask[i],
				 0);
	}

	/* Explicitely initialize control register */
	regs[JTAG_UART_CTRL_REG].value =
		(JTAG_UART_FIFO_SIZE <<	JTAG_UART_CTRL_WSPACE_OFF)
		& JTAG_UART_CTRL_WSPACE_MASK;

	ju->clk_count = JTAG_UART_CLK_COUNT_INIT;
	dev->priv = ju;

	return 0;
}

static bool jtag_uart_is_dev_addr(struct device *dev, uint32_t addr)
{
	struct jtag_uart *ju = dev->priv;
	unsigned int i;

	for (i = 0; i < JTAG_UART_REG_COUNT; i++)
		if (ju->regs[i].addr == addr)
			return true;

	return false;
}

static bool jtag_uart_has_irq(struct device *dev)
{
	struct jtag_uart *ju = dev->priv;
	uint32_t ctrl_val;

	ju->clk_count--;
	if (ju->clk_count > 0)
		return false;

	ctrl_val = ju->regs[JTAG_UART_CTRL_REG].value;

	/* handle write interrupt */
	if (ctrl_val & JTAG_UART_CTRL_WE_MASK)
		if ((ctrl_val & JTAG_UART_CTRL_WSPACE_MASK) != 0)
			return true;

	/* TODO: Read interrupt */

	return false;
}

static void jtag_uart_simulate(struct device *dev)
{
	struct jtag_uart *ju = dev->priv;
	struct io_register *regs = ju->regs;

	if (ju->tx_fifo.has_data) {
		jtag_uart_printf("%c", ju->tx_fifo.data);
		ju->tx_fifo.has_data = false;
		/* set available fifo size */
		regs[JTAG_UART_CTRL_REG].value |=
			(JTAG_UART_FIFO_SIZE <<	JTAG_UART_CTRL_WSPACE_OFF)
			& JTAG_UART_CTRL_WSPACE_MASK;

		if (regs[JTAG_UART_CTRL_REG].value & JTAG_UART_CTRL_WE_MASK)
			regs[JTAG_UART_CTRL_REG].value |= JTAG_UART_CTRL_WI_MASK;
	} else {
		if ((regs[JTAG_UART_CTRL_REG].value & JTAG_UART_CTRL_WSPACE_MASK) != 0
		    && (regs[JTAG_UART_CTRL_REG].value & JTAG_UART_CTRL_WE_MASK))
				regs[JTAG_UART_CTRL_REG].value |= JTAG_UART_CTRL_WI_MASK;
	}
}

struct device jtag_uart_core = {
	.name		= "JTAG UART Core",
	.base		= JTAG_UART_BASE,
	.size		= JTAG_UART_SIZE,
	.irq_mask	= IRQ_TO_MASK(IRQ_JTAG_UART),

	.init		= jtag_uart_init,
	.is_dev_addr	= jtag_uart_is_dev_addr,
	.has_irq	= jtag_uart_has_irq,
	.simulate	= jtag_uart_simulate,
};

#if 0
static uint32_t uart_read(struct io_device * self, uint32_t addr, uint32_t data_len)
{
	if (addr == priv.regs[JTAG_UART_CTRL_REG].addr){
		return priv.regs[JTAG_UART_CTRL_REG].value;
	}
	else if (addr == priv.regs[JTAG_UART_DATA_REG].addr){
		return priv.regs[JTAG_UART_DATA_REG].value;
	}

	return 0;
}

static void write_tx_fifo(uint32_t data)
{
	priv.tx_fifo.data = data & 0xFF;
	priv.tx_fifo.is_write = 1;
	/* clean WI bit */
	priv.regs[JTAG_UART_CTRL_REG].value &= (~ALTERA_JTAGUART_CONTROL_WI_MSK);
	/* clean write space bits */
	priv.regs[JTAG_UART_CTRL_REG].value &= 0xFFFF;
}

static void uart_write(struct io_device * self, uint32_t addr, uint32_t data, uint32_t data_len)
{
	int32_t i = 0;
	
    for (i=0;i<JTAG_UART_REG_COUNT;i++){
        if (priv.regs[i].addr == addr){
			if (i == JTAG_UART_DATA_REG){
				priv.regs[i].value = io_write_data(priv.regs[i].value, data, data_len);
				write_tx_fifo(data);
			}
			else if(i == JTAG_UART_CTRL_REG){
				priv.regs[i].value |= (io_write_data(priv.regs[i].value, data, data_len) & 0x3);
				/* if change the interrupt enable bits */
				if (data & 0x03){
					priv.regs[i].value = priv.regs[i].value & (~ALTERA_JTAGUART_CONTROL_WI_MSK);
				}
			}
        }
    }
}

static void jtag_uart_simulate(struct io_device * self)
{	
	/* if has data to send */
	if (priv.tx_fifo.is_write){
		printf("%c", priv.tx_fifo.data);
		priv.tx_fifo.is_write = 0;
		/* set available fifo size */
		priv.regs[JTAG_UART_CTRL_REG].value |= (JTAG_UART_FIFO_SIZE << ALTERA_JTAGUART_CONTROL_WSPACE_OFST);
		/* if set write interrupt enable */
		if (priv.regs[JTAG_UART_CTRL_REG].value & ALTERA_JTAGUART_CONTROL_WE_MSK){
			/* set write interrupt bit */
			priv.regs[JTAG_UART_CTRL_REG].value |= ALTERA_JTAGUART_CONTROL_WI_MSK;
		}
	}
	else {
		if (priv.regs[JTAG_UART_CTRL_REG].value & (JTAG_UART_FIFO_SIZE << ALTERA_JTAGUART_CONTROL_WSPACE_OFST)){
			/* if set write interrupt enable */
			if (priv.regs[JTAG_UART_CTRL_REG].value & ALTERA_JTAGUART_CONTROL_WE_MSK){
				/* set write interrupt bit */
				priv.regs[JTAG_UART_CTRL_REG].value |= ALTERA_JTAGUART_CONTROL_WI_MSK;
			}
		}
	}
}

struct io_device jtag_uart_io_device = {
	.name = "Jtag UART Core",
	.init = uart_init,
	.is_belong = uart_is_belong,
	.read_data = uart_read,
	.write_data = uart_write,
	.has_irq = jtag_uart_has_irq,
	.simulate = jtag_uart_simulate,
	.irq_enable_mask = JTAG_IRQ_MASK
};

#endif