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authorTobias Klauser <klto@zhaw.ch>2011-01-19 17:15:07 +0100
committerTobias Klauser <klto@zhaw.ch>2011-01-19 17:15:07 +0100
commitc913e05fb214dc84c2288626fd33ab6eea2789ab (patch)
tree26f9601e90c824ffade2dcde1dca6cc83bb73a27 /lib/ethernet
parent892d6e65fc7e09834b6f5d414773242052a5e869 (diff)
Update rmii_phy_to_mii_mac.vhd from upstream
Diffstat (limited to 'lib/ethernet')
-rw-r--r--lib/ethernet/components/rmii_phy_to_mii_mac.vhd19
1 files changed, 4 insertions, 15 deletions
diff --git a/lib/ethernet/components/rmii_phy_to_mii_mac.vhd b/lib/ethernet/components/rmii_phy_to_mii_mac.vhd
index 09227c6..56d5302 100644
--- a/lib/ethernet/components/rmii_phy_to_mii_mac.vhd
+++ b/lib/ethernet/components/rmii_phy_to_mii_mac.vhd
@@ -30,7 +30,7 @@ package rmii_phy_to_mii_mac_pkg is
reset_n_i : in std_logic;
clk_25_i : in std_logic;
clk_50_i : in std_logic;
- rmii_crs_i : in std_logic;
+ rmii_link_i : in std_logic;
-- Transmit Path
mii_tx_en_i : in std_logic;
@@ -56,7 +56,7 @@ entity rmii_phy_to_mii_mac is
reset_n_i : in std_logic;
clk_25_i : in std_logic;
clk_50_i : in std_logic;
- rmii_crs_i : in std_logic;
+ rmii_link_i : in std_logic;
-- Transmit Path
mii_tx_en_i : in std_logic;
@@ -75,8 +75,6 @@ end rmii_phy_to_mii_mac;
architecture behavior of rmii_phy_to_mii_mac is
- signal rmii_txd_next, rmii_txd_curr : std_logic;
- signal clk_25_sync_to_data : std_logic;
signal clk_25_toggle, clk_50_toggle : std_logic;
signal rmii_rxd_buffer : std_logic_vector(5 downto 0);
signal mii_txd_buffer : std_logic_vector(3 downto 0);
@@ -85,7 +83,6 @@ architecture behavior of rmii_phy_to_mii_mac is
signal rmii_rx_dv_f : std_logic;
signal mii_rx_dv_f : std_logic;
signal mii_rx_dv_ff : std_logic;
- signal rmii_valid_sof : std_logic;
begin
@@ -166,12 +163,8 @@ begin
mii_rxd_o <= (others => '0');
elsif rising_edge(clk_50_i) then
if clk_50_en = '1' then
-
- if rmii_valid_sof = '1' then --only valid if the packet from phy is valid
mii_rx_dv_f <= rmii_rx_dv_i;
mii_rx_dv_ff <= mii_rx_dv_f; -- valid is two 25 MHz clockcycles later
- end if;
-
if buffer_cnt = 1 then -- depends on the rmii dv signal
mii_rxd_o <= rmii_rxd_buffer(3 downto 0); -- Three step buffer
else
@@ -180,7 +173,7 @@ begin
end if;
end if;
end process;
- mii_rx_dv_o <= mii_rx_dv_ff ;
+ mii_rx_dv_o <= mii_rx_dv_ff;
-- counts the 50MHz clocks before rmii dv signal goes high before a 25MHZ Clock
buffer_cnt_proc: process (reset_n_i, clk_50_i)
@@ -196,16 +189,12 @@ begin
end if;
end process;
- rmii_valid_sof_proc: process (reset_n_i, clk_50_i)
+ input_register: process (reset_n_i, clk_50_i)
begin
if reset_n_i = '0' then
- rmii_valid_sof <= '0';
rmii_rx_dv_f <= '0';
elsif rising_edge(clk_50_i) then
rmii_rx_dv_f <= rmii_rx_dv_i;
- if rmii_crs_i = '1' and rmii_rx_dv_f = '0' and rmii_rx_dv_i = '1' then -- start of a valid frame
- rmii_valid_sof <= '1';
- end if;
end if;
end process;