ASoC: cs42xx8: Mark chip ID as volatile and remove cache bypass

Rather than manually enabling cache bypass when reading the ID registers
simply remove the default which will cause the first read to go to the
hardware. The old code worked this is simply the more standard way to
implement this. There is a comment included in the code that claims the
chip ID register also contains the right input volume, however this is
clearly not the case from the rest of the driver. Further investigation
reveals exactly the same comment in the wm8962 driver, where this is the
case, so this is almost certainly a copy and paste error from when the
driver was created.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

1 files changed, 9 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
index 5299300..3311204 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,5 +8,14 @@ quartus/*.summary
 
 # VHDL created by SOPC builder
 quartus/cpu_0*
+quartus/descriptor_memory.vhd
+quartus/jtag_uart_0.vhd
+quartus/onchip_memory2_0.vhd
+quartus/sdram_0.vhd
+quartus/sgdma_rx.vhd
+quartus/sgdma_tx.vhd
+quartus/sysid.vhd
+quartus/timer_0.vhd
 quartus/tse_mac*.vhd
+quartus/uart_0.vhd
 quartus/watchdog_timer.vhd