diff options
| -rw-r--r-- | quartus/dionysos_nios2mmu.qsf | 1 | ||||
| -rw-r--r-- | quartus/dionysos_nios2mmu.sdc | 13 |
2 files changed, 13 insertions, 1 deletions
diff --git a/quartus/dionysos_nios2mmu.qsf b/quartus/dionysos_nios2mmu.qsf index 925dfed..a51bd81 100644 --- a/quartus/dionysos_nios2mmu.qsf +++ b/quartus/dionysos_nios2mmu.qsf @@ -434,6 +434,7 @@ set_global_assignment -name VHDL_FILE ../lib/misc/components/reset_sync.vhd set_global_assignment -name VHDL_FILE ../dionysos_top.vhd set_global_assignment -name QIP_FILE dionysos_nios2mmu.qip set_global_assignment -name VHDL_FILE dionysos_nios2mmu.vhd +set_global_assignment -name SDC_FILE dionysos_nios2mmu.sdc set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/quartus/dionysos_nios2mmu.sdc b/quartus/dionysos_nios2mmu.sdc index a4948ef..dab2e78 100644 --- a/quartus/dionysos_nios2mmu.sdc +++ b/quartus/dionysos_nios2mmu.sdc @@ -27,6 +27,18 @@ create_clock -name epcs_rd_clk -period 20MHz -add [get_ports config_dclk_o] # Create Generated Clock (Used for Clock relations (PLL)) #************************************************************** +# connected via PLL (Normal Mode) +create_generated_clock -name pll_1_clk_0 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ + [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[0]}] + +# connected via PLL (Normal Mode, Divided by 2) +create_generated_clock -name pll_1_clk_1 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ + -divide_by 2 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[1]}] + +# connected via PLL (Normal Mode, Divided by 4) +create_generated_clock -name pll_1_clk_2 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ + -divide_by 4 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[2]}] + # connected via PLL (Normal Mode, -3ns phase shift create_generated_clock -name pll_1_clk_3 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ -phase -54.000 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[3]}] @@ -39,7 +51,6 @@ create_generated_clock -name clock_dram -source [get_pins {sinet_pll|alt # Set Clock Groups #************************************************************** - # EPCS16N-98364 (EPCS): cut all paths between the write and read clock (just one of both is active at any time) set_clock_groups -asynchronous -group [get_clocks epcs_wd_clk] -group [get_clocks epcs_rd_clk] -group [get_clocks {pll_1_clk_0}] |