diff options
| -rw-r--r-- | devicetree/dionysos_nios2mmu.dtb | bin | 0 -> 3658 bytes | |||
| -rw-r--r-- | devicetree/dionysos_nios2mmu.dts | 167 |
2 files changed, 167 insertions, 0 deletions
diff --git a/devicetree/dionysos_nios2mmu.dtb b/devicetree/dionysos_nios2mmu.dtb Binary files differnew file mode 100644 index 0000000..a5fc09e --- /dev/null +++ b/devicetree/dionysos_nios2mmu.dtb diff --git a/devicetree/dionysos_nios2mmu.dts b/devicetree/dionysos_nios2mmu.dts new file mode 100644 index 0000000..8dacceb --- /dev/null +++ b/devicetree/dionysos_nios2mmu.dts @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2010 Walter Goossens <waltergoossens@home.nl>. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +/dts-v1/; +/ { + model = "altera,dionysos_nios2mmu"; + compatible = "altera,dionysos_nios2mmu"; + #address-cells = <1>; + #size-cells = <1>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu_0: cpu@0x0 { + device-type = "cpu"; + compatible = "altera,nios2"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + clock-frequency = <50000000>; + d-cache-block-size = <32>; + i-cache-block-size = <32>; + d-cache-size = <2048>; + i-cache-size = <4096>; + }; + }; + memory@0 { + device-type = "memory"; + reg = <0x01000000 0x01000000 + 0x02802000 0x00000400 + 0x04840000 0x00002000>; + }; + sopc@0 { + #address-cells = <1>; + #size-cells = <1>; + device-type = "soc"; + compatible = "altera,avalon","simple-bus"; + ranges ; + bus-frequency = < 50000000 >; + //Port instruction_master of cpu_0 + epcs_flash_controller_0: flash@0x2801800 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "altera,epcs_flash", "epcs-flash"; + reg = <0x2801800 0x800>; + interrupt-parent = < &cpu_0 >; + interrupts = <1>; + bank-width = <2>; + device-width = <1>; + dtb@0 { + reg = < 0x00000000 0x00020000 >; + read-only; + }; + fpga@20000 { + reg = < 0x00020000 0x00160000 >; + read-only; + }; + kernel@180000 { + reg = < 0x00180000 0x00280000 >; + read-only; + }; + rootfs@400000 { + reg = < 0x00400000 0x00C00000 >; + }; + }; //end flash (epcs_flash_controller_0) + + cfi_flash_0: flash@0x2400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "altera,cfi_flash", "cfi-flash"; + reg = <0x2400000 0x400000>; + bank-width = <1>; + device-width = <1>; + dtb@0 { + reg = < 0x00000000 0x00020000 >; + read-only; + }; + fpga@20000 { + reg = < 0x00020000 0x00160000 >; + read-only; + }; + kernel@180000 { + reg = < 0x00180000 0x00280000 >; + read-only; + }; + rootfs@400000 { + reg = < 0x00400000 0x00C00000 >; + }; + }; //end flash (cfi_flash_0) + + //Port tightly_coupled_instruction_master_0 of cpu_0 + //Port data_master of cpu_0 + timer_0: unknown@0x2802880 { + compatible = "unknown,unknown"; + reg = <0x2802880 0x8>; + interrupt-parent = < &cpu_0 >; + interrupts = <0>; + }; //end unknown (timer_0) + + uart_0: serial@0x28028a0 { + compatible = "altera,altera_uart"; + reg = <0x28028a0 0x8>; + interrupt-parent = < &cpu_0 >; + interrupts = <2>; + current-speed = <115200>; + clock-frequency = <50000000>; + }; //end serial (uart_0) + + jtag_uart_0: serial@0x28028c0 { + compatible = "altera,altera_juart"; + reg = <0x28028c0 0x2>; + interrupt-parent = < &cpu_0 >; + interrupts = <3>; + }; //end serial (jtag_uart_0) + + tse_mac: ethernet@0x2802400 { + compatible = "altera,tse"; + reg = <0x2802400 0x400>; + altera,sgdma_tx = < &sgdma_tx >; + altera,sgdma_rx = < &sgdma_rx >; + }; //end ethernet (tse_mac) + + sgdma_rx: dma@0x2802800 { + compatible = "altera,alt_sgdma"; + reg = <0x2802800 0x40>; + interrupt-parent = < &cpu_0 >; + interrupts = <4>; + type = < 2 >; //STREAM_TO_MEMORY + }; //end dma (sgdma_rx) + + sgdma_tx: dma@0x2802840 { + compatible = "altera,alt_sgdma"; + reg = <0x2802840 0x40>; + interrupt-parent = < &cpu_0 >; + interrupts = <5>; + type = < 1 >; //MEMORY_TO_STREAM + }; //end dma (sgdma_tx) + + watchdog_timer: watchdog@0x4880000 { + compatible = "altera,altera_wdt"; + reg = <0x4880000 0x8>; + interrupt-parent = < &cpu_0 >; + interrupts = <6>; + clock-frequency = <50000000>; + }; //end watchdog (watchdog_timer) + + //Port tightly_coupled_data_master_0 of cpu_0 + }; //sopc + chosen { + bootargs = "debug console=ttyAL0,115200"; + }; +}; |