diff options
Diffstat (limited to 'dionysos_top.vhd')
| -rw-r--r-- | dionysos_top.vhd | 60 |
1 files changed, 50 insertions, 10 deletions
diff --git a/dionysos_top.vhd b/dionysos_top.vhd index 88f8e1f..19dd923 100644 --- a/dionysos_top.vhd +++ b/dionysos_top.vhd @@ -208,19 +208,20 @@ entity dionysos_top is --! \anchor mdio_grp et_phy2_mdc_o : out std_logic; --! Dual eth phy1, phy2 Management clock et_phy2_mdio_io : inout std_logic; --! Dual eth phy1, phy2 data - rst_et_phy2_n_o : out std_logic --! Ethernet phy reset + rst_et_phy2_n_o : out std_logic; --! Ethernet phy reset --@} + gpio_o : out std_logic_vector(1 downto 0); + gpio_i : in std_logic_vector(1 downto 0) ); end dionysos_top; architecture rtl of dionysos_top is - --! FPGA main clock frequency (50MHz) - constant C_FPGA_FREQ : integer := 50000000; - --! front pannel LEDs - signal leds : std_logic_vector(15 downto 0); + signal leds_front : std_logic_vector(13 downto 0); + --! board LEDs + signal leds_board : std_logic_vector(3 downto 0); --! @name SDRAM Data --@{ @@ -319,7 +320,9 @@ architecture rtl of dionysos_top is signal mac_mdio_en_n : std_logic; --@} - begin + signal gpio_sync_in : std_logic_vector(gpio_i'range); + +begin --! @name Components --@{ @@ -376,10 +379,43 @@ architecture rtl of dionysos_top is reset_n_o => fpga_reset_n_ff_100 -- reset 100 clocks delayed ); - gen_led_g_o <= (others => '1'); - gen_led_r_o <= (others => '1'); + -- + -- GPIO Input synchronization + -- + gpio_sync_gen : for i in gpio_i'range generate + gpio_in_sync : entity work.input_sync + generic map( + G_INIT_VALUE => '0' + ) + port map( + clk_i => pll_clk_50, + reset_n_i => reset_n, + async_signal_i => gpio_i(i), + sync_signal_o => gpio_sync_in(i) + ); + end generate gpio_sync_gen; + + -- + -- Synchronize DIP switches + -- + sw_syncer : entity ines_misc.buf_sync + generic map( + G_NUM_BUF => sw_sync'length + ) + port map( + clk_i => pll_clk_50, + reset_n_i => reset_n, + inp_i => switch_i(sw_sync'range), + outp_o => sw_sync + ); + + -- + -- LEDs + -- - gp_led_o <= (others => '1'); + gen_led_g_o <= not leds_front(6 downto 0); + gen_led_r_o <= not leds_front(13 downto 7); + gp_led_o <= not leds_board; -- NIOSII CPU flash_reset_n_o <= '1'; @@ -472,8 +508,12 @@ architecture rtl of dionysos_top is OTG_RST_N_from_the_ISP1362 => otg_reset_n_o, OTG_WR_N_from_the_ISP1362 => otg_we_n_o, OTG_INT0_to_the_ISP1362 => otg_int0_i, - OTG_INT1_to_the_ISP1362 => otg_int1_i + OTG_INT1_to_the_ISP1362 => otg_int1_i, + -- GPIO + out_port_from_the_pio_leds_front => leds_front, + out_port_from_the_pio_leds_board => leds_board, + in_port_to_the_pio_dipswitch => sw_sync ); --------------------------------------------------------------------- |