diff options
Diffstat (limited to 'quartus/dionysos_nios2mmu.sopc')
| -rw-r--r-- | quartus/dionysos_nios2mmu.sopc | 566 |
1 files changed, 566 insertions, 0 deletions
diff --git a/quartus/dionysos_nios2mmu.sopc b/quartus/dionysos_nios2mmu.sopc new file mode 100644 index 0000000..6bbc587 --- /dev/null +++ b/quartus/dionysos_nios2mmu.sopc @@ -0,0 +1,566 @@ +<?xml version="1.0" encoding="UTF-8"?> +<system name="dionysos_nios2mmu"> + <parameter name="bonusData"><![CDATA[bonusData +{ + element jtag_uart_0.avalon_jtag_slave + { + datum baseAddress + { + value = "41951296"; + type = "long"; + } + } + element cfi_flash_0 + { + datum _sortIndex + { + value = "5"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos-nios2mmu}"; + type = "String"; + } + } + element clk_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element cpu_0 + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element dionysos_nios2mmu + { + } + element epcs_flash_controller_0.epcs_control_port + { + datum baseAddress + { + value = "41949184"; + type = "long"; + } + } + element epcs_flash_controller_0 + { + datum _sortIndex + { + value = "7"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element cpu_0.jtag_debug_module + { + datum baseAddress + { + value = "41947136"; + type = "long"; + } + } + element jtag_uart_0 + { + datum _sortIndex + { + value = "9"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element onchip_memory2_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element onchip_memory2_0.s1 + { + datum baseAddress + { + value = "4096"; + type = "long"; + } + } + element timer_0.s1 + { + datum baseAddress + { + value = "41951232"; + type = "long"; + } + } + element uart_0.s1 + { + datum baseAddress + { + value = "41951264"; + type = "long"; + } + } + element sdram_0.s1 + { + datum _lockedAddress + { + value = "0"; + type = "boolean"; + } + datum baseAddress + { + value = "16777216"; + type = "long"; + } + } + element cfi_flash_0.s1 + { + datum baseAddress + { + value = "37748736"; + type = "long"; + } + } + element sdram_0 + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos-nios2mmu}"; + type = "String"; + } + } + element timer_0 + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element tri_state_bridge_0 + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element uart_0 + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } +} +]]></parameter> + <parameter name="deviceFamily" value="CYCLONEIII" /> + <parameter name="generateLegacySim" value="false" /> + <parameter name="hardcopyCompatible" value="false" /> + <parameter name="hdlLanguage" value="VHDL" /> + <parameter name="projectName">dionysos-nios2mmu.qpf</parameter> + <parameter name="systemHash" value="-19653124377" /> + <parameter name="timeStamp" value="1269273057814" /> + <module name="clk_0" kind="clock_source" version="9.1" enabled="1"> + <parameter name="clockFrequency" value="50000000" /> + <parameter name="clockFrequencyKnown" value="true" /> + </module> + <module name="cpu_0" kind="altera_nios2" version="9.1" enabled="1"> + <parameter name="userDefinedSettings" value="" /> + <parameter name="setting_showUnpublishedSettings" value="false" /> + <parameter name="setting_showInternalSettings" value="false" /> + <parameter name="setting_shadowRegisterSets" value="0" /> + <parameter name="setting_preciseSlaveAccessErrorException" value="false" /> + <parameter name="setting_preciseIllegalMemAccessException" value="false" /> + <parameter name="setting_preciseDivisionErrorException" value="false" /> + <parameter name="setting_performanceCounter" value="false" /> + <parameter name="setting_perfCounterWidth" value="_32" /> + <parameter name="setting_interruptControllerType" value="Internal" /> + <parameter name="setting_illegalMemAccessDetection" value="false" /> + <parameter name="setting_illegalInstructionsTrap" value="false" /> + <parameter name="setting_fullWaveformSignals" value="false" /> + <parameter name="setting_extraExceptionInfo" value="false" /> + <parameter name="setting_exportPCB" value="false" /> + <parameter name="setting_debugSimGen" value="false" /> + <parameter name="setting_clearXBitsLDNonBypass" value="true" /> + <parameter name="setting_branchPredictionType" value="Automatic" /> + <parameter name="setting_bit31BypassDCache" value="true" /> + <parameter name="setting_bigEndian" value="false" /> + <parameter name="setting_bhtPtrSz" value="_8" /> + <parameter name="setting_bhtIndexPcOnly" value="false" /> + <parameter name="setting_avalonDebugPortPresent" value="false" /> + <parameter name="setting_alwaysEncrypt" value="true" /> + <parameter name="setting_allowFullAddressRange" value="false" /> + <parameter name="setting_activateTrace" value="true" /> + <parameter name="setting_activateTestEndChecker" value="false" /> + <parameter name="setting_activateMonitors" value="true" /> + <parameter name="setting_activateModelChecker" value="false" /> + <parameter name="setting_HDLSimCachesCleared" value="true" /> + <parameter name="setting_HBreakTest" value="false" /> + <parameter name="resetSlave" value="cfi_flash_0.s1" /> + <parameter name="resetOffset" value="0" /> + <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" /> + <parameter name="muldiv_divider" value="false" /> + <parameter name="mpu_useLimit" value="false" /> + <parameter name="mpu_numOfInstRegion" value="8" /> + <parameter name="mpu_numOfDataRegion" value="8" /> + <parameter name="mpu_minInstRegionSize" value="_12" /> + <parameter name="mpu_minDataRegionSize" value="_12" /> + <parameter name="mpu_enabled" value="false" /> + <parameter name="mmu_uitlbNumEntries" value="_4" /> + <parameter name="mmu_udtlbNumEntries" value="_6" /> + <parameter name="mmu_tlbPtrSz" value="_7" /> + <parameter name="mmu_tlbNumWays" value="_16" /> + <parameter name="mmu_processIDNumBits" value="_8" /> + <parameter name="mmu_enabled" value="true" /> + <parameter name="mmu_autoAssignTlbPtrSz" value="true" /> + <parameter name="mmu_TLBMissExcSlave" value="onchip_memory2_0.s1" /> + <parameter name="mmu_TLBMissExcOffset" value="0" /> + <parameter name="manuallyAssignCpuID" value="false" /> + <parameter name="impl" value="Fast" /> + <parameter name="icache_size" value="_4096" /> + <parameter name="icache_ramBlockType" value="Automatic" /> + <parameter name="icache_numTCIM" value="_1" /> + <parameter name="icache_burstType" value="None" /> + <parameter name="exceptionSlave" value="sdram_0.s1" /> + <parameter name="exceptionOffset" value="32" /> + <parameter name="debug_triggerArming" value="true" /> + <parameter name="debug_level" value="Level1" /> + <parameter name="debug_jtagInstanceID" value="0" /> + <parameter name="debug_embeddedPLL" value="true" /> + <parameter name="debug_debugReqSignals" value="false" /> + <parameter name="debug_assignJtagInstanceID" value="false" /> + <parameter name="debug_OCIOnchipTrace" value="_128" /> + <parameter name="dcache_size" value="_2048" /> + <parameter name="dcache_ramBlockType" value="Automatic" /> + <parameter name="dcache_omitDataMaster" value="false" /> + <parameter name="dcache_numTCDM" value="_1" /> + <parameter name="dcache_lineSize" value="_32" /> + <parameter name="dcache_bursts" value="false" /> + <parameter name="cpuReset" value="false" /> + <parameter name="cpuID" value="0" /> + <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter> + <parameter name="breakOffset" value="32" /> + </module> + <module + name="sdram_0" + kind="altera_avalon_new_sdram_controller" + version="9.1" + enabled="1"> + <parameter name="TAC" value="5.5" /> + <parameter name="TMRD" value="3" /> + <parameter name="TRCD" value="20.0" /> + <parameter name="TRFC" value="70.0" /> + <parameter name="TRP" value="20.0" /> + <parameter name="TWR" value="14.0" /> + <parameter name="casLatency" value="3" /> + <parameter name="columnWidth" value="9" /> + <parameter name="dataWidth" value="16" /> + <parameter name="generateSimulationModel" value="true" /> + <parameter name="initNOPDelay" value="0.0" /> + <parameter name="initRefreshCommands" value="2" /> + <parameter name="masteredTristateBridgeSlave" value="" /> + <parameter name="model" value="custom" /> + <parameter name="numberOfBanks" value="4" /> + <parameter name="numberOfChipSelects" value="1" /> + <parameter name="pinsSharedViaTriState" value="false" /> + <parameter name="powerUpDelay" value="100.0" /> + <parameter name="refreshPeriod" value="15.625" /> + <parameter name="registerDataIn" value="true" /> + <parameter name="rowWidth" value="12" /> + </module> + <module + name="tri_state_bridge_0" + kind="altera_avalon_tri_state_bridge" + version="9.1" + enabled="1"> + <parameter name="registerIncomingSignals" value="true" /> + </module> + <module + name="cfi_flash_0" + kind="altera_avalon_cfi_flash" + version="9.1" + enabled="1"> + <parameter name="addressWidth" value="22" /> + <parameter name="corePreset" value="CUSTOM" /> + <parameter name="dataWidth" value="8" /> + <parameter name="holdTime" value="40" /> + <parameter name="setupTime" value="40" /> + <parameter name="sharedPorts">s1/address,s1/data,s1/read_n</parameter> + <parameter name="timingUnits" value="NS" /> + <parameter name="waitTime" value="160" /> + </module> + <module + name="epcs_flash_controller_0" + kind="altera_avalon_epcs_flash_controller" + version="9.1" + enabled="1"> + <parameter name="autoSelectASMIAtom" value="true" /> + <parameter name="useASMIAtom" value="false" /> + </module> + <module name="timer_0" kind="altera_avalon_timer" version="9.1" enabled="1"> + <parameter name="alwaysRun" value="false" /> + <parameter name="counterSize" value="32" /> + <parameter name="fixedPeriod" value="false" /> + <parameter name="period" value="1" /> + <parameter name="periodUnits" value="MSEC" /> + <parameter name="resetOutput" value="false" /> + <parameter name="snapshot" value="true" /> + <parameter name="timeoutPulseOutput" value="false" /> + <parameter name="timerPreset" value="CUSTOM" /> + </module> + <module name="uart_0" kind="altera_avalon_uart" version="9.1" enabled="1"> + <parameter name="baud" value="115200" /> + <parameter name="dataBits" value="8" /> + <parameter name="fixedBaud" value="true" /> + <parameter name="parity" value="NONE" /> + <parameter name="simCharStream" value="" /> + <parameter name="simInteractiveInputEnable" value="false" /> + <parameter name="simInteractiveOutputEnable" value="false" /> + <parameter name="simTrueBaud" value="false" /> + <parameter name="stopBits" value="1" /> + <parameter name="syncRegDepth" value="2" /> + <parameter name="useCtsRts" value="false" /> + <parameter name="useEopRegister" value="false" /> + <parameter name="useRelativePathForSimFile" value="false" /> + </module> + <module + name="jtag_uart_0" + kind="altera_avalon_jtag_uart" + version="9.1" + enabled="1"> + <parameter name="allowMultipleConnections" value="false" /> + <parameter name="hubInstanceID" value="0" /> + <parameter name="readBufferDepth" value="64" /> + <parameter name="readIRQThreshold" value="8" /> + <parameter name="simInputCharacterStream" value="" /> + <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter> + <parameter name="useRegistersForReadBuffer" value="false" /> + <parameter name="useRegistersForWriteBuffer" value="false" /> + <parameter name="useRelativePathForSimFile" value="false" /> + <parameter name="writeBufferDepth" value="64" /> + <parameter name="writeIRQThreshold" value="8" /> + </module> + <module + name="onchip_memory2_0" + kind="altera_avalon_onchip_memory2" + version="9.1" + enabled="1"> + <parameter name="allowInSystemMemoryContentEditor" value="false" /> + <parameter name="blockType" value="AUTO" /> + <parameter name="dataWidth" value="32" /> + <parameter name="dualPort" value="true" /> + <parameter name="initMemContent" value="true" /> + <parameter name="initializationFileName" value="onchip_memory2_0" /> + <parameter name="instanceID" value="NONE" /> + <parameter name="memorySize" value="1024" /> + <parameter name="readDuringWriteMode" value="DONT_CARE" /> + <parameter name="simAllowMRAMContentsFile" value="false" /> + <parameter name="slave1Latency" value="1" /> + <parameter name="slave2Latency" value="1" /> + <parameter name="useNonDefaultInitFile" value="false" /> + <parameter name="useShallowMemBlocks" value="false" /> + <parameter name="writable" value="true" /> + </module> + <connection kind="clock" version="9.1" start="clk_0.clk" end="cpu_0.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.instruction_master" + end="cpu_0.jtag_debug_module"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02801000" /> + </connection> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="cpu_0.jtag_debug_module"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02801000" /> + </connection> + <connection kind="clock" version="9.1" start="clk_0.clk" end="sdram_0.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.instruction_master" + end="sdram_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x01000000" /> + </connection> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="sdram_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x01000000" /> + </connection> + <connection + kind="clock" + version="9.1" + start="clk_0.clk" + end="tri_state_bridge_0.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.instruction_master" + end="tri_state_bridge_0.avalon_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + </connection> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="tri_state_bridge_0.avalon_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + </connection> + <connection kind="clock" version="9.1" start="clk_0.clk" end="cfi_flash_0.clk" /> + <connection + kind="avalon_tristate" + version="9.1" + start="tri_state_bridge_0.tristate_master" + end="cfi_flash_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02400000" /> + </connection> + <connection + kind="clock" + version="9.1" + start="clk_0.clk" + end="epcs_flash_controller_0.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.instruction_master" + end="epcs_flash_controller_0.epcs_control_port"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02801800" /> + </connection> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="epcs_flash_controller_0.epcs_control_port"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02801800" /> + </connection> + <connection + kind="interrupt" + version="9.1" + start="cpu_0.d_irq" + end="epcs_flash_controller_0.irq"> + <parameter name="irqNumber" value="1" /> + </connection> + <connection kind="clock" version="9.1" start="clk_0.clk" end="timer_0.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="timer_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02802000" /> + </connection> + <connection kind="interrupt" version="9.1" start="cpu_0.d_irq" end="timer_0.irq"> + <parameter name="irqNumber" value="0" /> + </connection> + <connection kind="clock" version="9.1" start="clk_0.clk" end="uart_0.clk" /> + <connection kind="avalon" version="6.1" start="cpu_0.data_master" end="uart_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02802020" /> + </connection> + <connection kind="interrupt" version="9.1" start="cpu_0.d_irq" end="uart_0.irq"> + <parameter name="irqNumber" value="2" /> + </connection> + <connection kind="clock" version="9.1" start="clk_0.clk" end="jtag_uart_0.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="jtag_uart_0.avalon_jtag_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02802040" /> + </connection> + <connection + kind="interrupt" + version="9.1" + start="cpu_0.d_irq" + end="jtag_uart_0.irq"> + <parameter name="irqNumber" value="3" /> + </connection> + <connection + kind="clock" + version="9.1" + start="clk_0.clk" + end="onchip_memory2_0.clk1" /> + <connection + kind="clock" + version="9.1" + start="clk_0.clk" + end="onchip_memory2_0.clk2" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.tightly_coupled_instruction_master_0" + end="onchip_memory2_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x1000" /> + </connection> + <connection + kind="avalon" + version="6.1" + start="cpu_0.tightly_coupled_data_master_0" + end="onchip_memory2_0.s2"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + </connection> +</system> |