blob: dea80fdd1e65d89543fa1931962d5226496b2e27 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
|
# TCL File Generated by Component Editor 8.0
# Thu Nov 20 17:00:55 CET 2008
# DO NOT MODIFY
# +-----------------------------------
# |
# | ISP1362_CTRL "ISP1362_CTRL" v1.0
# | null 2008.11.20.17:00:55
# |
# |
# | /home/scratch/testSystem/ISP1362_CTRL.v
# |
# | ./ISP1362_CTRL.v syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | module ISP1362_CTRL
# |
set_module_property NAME ISP1362_CTRL
set_module_property VERSION 1.0
set_module_property GROUP ""
set_module_property DISPLAY_NAME ISP1362_CTRL
set_module_property TOP_LEVEL_HDL_FILE ISP1362_CTRL.v
set_module_property TOP_LEVEL_HDL_MODULE ISP1362_CTRL
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE false
set_module_property SIMULATION_MODEL_IN_VERILOG false
set_module_property SIMULATION_MODEL_IN_VHDL false
set_module_property SIMULATION_MODEL_HAS_TULIPS false
set_module_property SIMULATION_MODEL_IS_OBFUSCATED false
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file ISP1362_CTRL.v {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clock_reset
# |
add_interface clock_reset clock end
set_interface_property clock_reset ptfSchematicName ""
add_interface_port clock_reset clk clk Input 1
add_interface_port clock_reset reset_n reset_n Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point avalon_slave_0
# |
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 holdTime 100
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
set_interface_property avalon_slave_0 bridgesToMaster ""
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 addressSpan 4
set_interface_property avalon_slave_0 timingUnits Nanoseconds
set_interface_property avalon_slave_0 setupTime 100
set_interface_property avalon_slave_0 writeWaitTime 100
set_interface_property avalon_slave_0 writeWaitStates 100
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 addressAlignment NATIVE
set_interface_property avalon_slave_0 readWaitStates 100
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 readWaitTime 100
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset
add_interface_port avalon_slave_0 address address Input 2
add_interface_port avalon_slave_0 readdata readdata Output 16
add_interface_port avalon_slave_0 writedata writedata Input 16
add_interface_port avalon_slave_0 chipselect_n chipselect_n Input 1
add_interface_port avalon_slave_0 read_n read_n Input 1
add_interface_port avalon_slave_0 write_n write_n Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point avalon_slave_1
# |
add_interface avalon_slave_1 avalon end
set_interface_property avalon_slave_1 holdTime 100
set_interface_property avalon_slave_1 linewrapBursts false
set_interface_property avalon_slave_1 minimumUninterruptedRunLength 1
set_interface_property avalon_slave_1 bridgesToMaster ""
set_interface_property avalon_slave_1 isMemoryDevice false
set_interface_property avalon_slave_1 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_1 timingUnits Nanoseconds
set_interface_property avalon_slave_1 setupTime 100
set_interface_property avalon_slave_1 writeWaitTime 100
set_interface_property avalon_slave_1 writeWaitStates 100
set_interface_property avalon_slave_1 isNonVolatileStorage false
set_interface_property avalon_slave_1 addressAlignment NATIVE
set_interface_property avalon_slave_1 readWaitStates 100
set_interface_property avalon_slave_1 maximumPendingReadTransactions 0
set_interface_property avalon_slave_1 readWaitTime 100
set_interface_property avalon_slave_1 readLatency 0
set_interface_property avalon_slave_1 printableDevice false
set_interface_property avalon_slave_1 ASSOCIATED_CLOCK clock_reset
add_interface_port avalon_slave_1 write_n_avalon_slave_1 write_n Input 1
add_interface_port avalon_slave_1 writedata_avalon_slave_1 writedata Input 8
# |
# +-----------------------------------
# +-----------------------------------
# | connection point conduit_end
# |
add_interface conduit_end conduit end
set_interface_property conduit_end ASSOCIATED_CLOCK clock_reset
add_interface_port conduit_end OTG_ADDR export Output 2
add_interface_port conduit_end OTG_DATA export Bidir 16
add_interface_port conduit_end OTG_CS_N export Output 1
add_interface_port conduit_end OTG_RD_N export Output 1
add_interface_port conduit_end OTG_WR_N export Output 1
add_interface_port conduit_end OTG_RST_N export Output 1
add_interface_port conduit_end OTG_INT0 export Input 1
add_interface_port conduit_end OTG_INT1 export Input 1
add_interface_port conduit_end OTG_FSPEED export Output 1
add_interface_port conduit_end OTG_LSPEED export Output 1
add_interface_port conduit_end OTG_DACK0_N export Output 1
add_interface_port conduit_end OTG_DACK1_N export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point interrupt_sender_1
# |
add_interface interrupt_sender_1 interrupt end
set_interface_property interrupt_sender_1 associatedAddressablePoint avalon_slave_1
set_interface_property interrupt_sender_1 ASSOCIATED_CLOCK clock_reset
add_interface_port interrupt_sender_1 irq_n_avalon_slave_1 irq_n Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point interrupt_sender_0
# |
add_interface interrupt_sender_0 interrupt end
set_interface_property interrupt_sender_0 associatedAddressablePoint avalon_slave_0
set_interface_property interrupt_sender_0 ASSOCIATED_CLOCK clock_reset
add_interface_port interrupt_sender_0 irq_n irq_n Output 1
# |
# +-----------------------------------
|