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------------------------------------------------------------------
-- _____ ______ _____ -
-- |_ _| | ____|/ ____| Institute of Embedded Systems -
-- | | _ __ | |__ | (___ Zuercher Hochschule fuer -
-- | | | '_ \| __| \___ \ angewandte Wissenschaften -
-- _| |_| | | | |____ ____) | (University of Applied Sciences) -
-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
------------------------------------------------------------------
--
-- Project : InES library
-- Module : library ines_misc
-- Description : port buffer with clock domain syncronisation
--
-- $LastChangedDate$
-- $Rev $
-- $Author $
-----------------------------------------------------------------
--
-- Change History
-- Date |Name |Modification
------------|----------|-----------------------------------------
-- 20.06.08 | ffar |file created
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package buf_sync_pkg is
component buf_sync
generic(
G_NUM_BUF : natural := 1
);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
inp_i : in std_logic_vector(G_NUM_BUF-1 downto 0);
outp_o : out std_logic_vector(G_NUM_BUF-1 downto 0)
);
end component buf_sync;
end package buf_sync_pkg;
library ieee;
use ieee.std_logic_1164.all;
entity buf_sync is
generic(
G_NUM_BUF : natural := 1
);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
inp_i : in std_logic_vector(G_NUM_BUF-1 downto 0);
outp_o : out std_logic_vector(G_NUM_BUF-1 downto 0)
);
end buf_sync;
architecture rtl of buf_sync is
signal inp_f : std_logic_vector(inp_i'range);
signal inp_ff : std_logic_vector(inp_i'range);
begin
outp_o <= inp_ff;
ff_gen : for i in inp_i'range generate
begin
ff_prc : process(clk_i, reset_n_i)
begin
if reset_n_i = '0' then
inp_f(i) <= '0';
inp_ff(i) <= '0';
elsif clk_i'event and clk_i = '1' then -- Creates the flipflops
inp_f(i) <= inp_i(i);
inp_ff(i) <= inp_f(i);
end if;
end process ff_prc;
end generate ff_gen;
end rtl;
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