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------------------------------------------------------------------
-- _____ ______ _____ -
-- |_ _| | ____|/ ____| Institute of Embedded Systems -
-- | | _ __ | |__ | (___ Zuercher Hochschule fuer -
-- | | | '_ \| __| \___ \ angewandte Wissenschaften -
-- _| |_| | | | |____ ____) | (University of Applied Sciences) -
-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
------------------------------------------------------------------
--
-- Project : SInet
-- Module : synthesis library ines_misc
-- Description : reset synchronisytion
--
-- $LastChangedDate: 2008-10-31 12:06:00 +0100 (Fri, 31 Oct 2008) $
-- $Rev: 1905 $
-- $Author: ffar $
-----------------------------------------------------------------
--
-- Change History
-- Date |Name |Modification
-----------------------------------------------------------------
-- 02.11.07 | ffar | file created based on library component
-- 24.06.08 | kelt | resets synchronized
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package reset_sync_pkg is
component reset_sync
generic(
STAGES : integer := 4
);
port(
clk_i : in std_logic;
reset1_n_i : in std_logic;
reset2_n_i : in std_logic := '1';
reset_n_o : out std_logic := '0'
);
end component reset_sync;
end package reset_sync_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_sync is
generic(
STAGES : integer := 4
);
port(
clk_i : in std_logic;
reset1_n_i : in std_logic;
reset2_n_i : in std_logic := '1';
reset_n_o : out std_logic := '0'
);
end reset_sync;
architecture rtl of reset_sync is
signal reset1_n_f, reset1_n_ff : std_logic;
signal reset2_n_f, reset2_n_ff : std_logic;
begin
reset_prc : process(clk_i)
variable count : integer range 0 to STAGES-1 := 0;
begin
if clk_i'event and clk_i = '1' then
reset1_n_f <= reset1_n_i;
reset1_n_ff <= reset1_n_f;
reset2_n_f <= reset2_n_i;
reset2_n_ff <= reset2_n_f;
if (reset1_n_ff and reset2_n_ff) = '0' then
reset_n_o <= '0';
count := 0;
elsif count < STAGES-1 then
reset_n_o <= '0';
count := count + 1;
else
reset_n_o <= '1';
end if;
end if;
end process reset_prc;
end rtl;
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