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##
## DEVICE  "EP3C40F484C6"
##

#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {clock_50}         -period 20.000 [get_ports {clock_50_i}]

# Write and Read Clock for the EPCS16N-98364 device
#----------------------
create_clock -name epcs_wd_clk -period 25MHz [get_ports config_dclk_o]
create_clock -name epcs_rd_clk -period 20MHz -add [get_ports config_dclk_o]

# JTAG: constrain the TCK port [Quartus II TimeQuest Timing Analyzer Cookbook]
#-----------------------------------------------------------------------------
#create_clock -name tck -period 10MHz [get_ports altera_reserved_tck]

#**************************************************************
# Create Generated Clock (Used for Clock relations (PLL))
#**************************************************************

# connected via PLL (Normal Mode)
create_generated_clock -name pll_1_clk_0        -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \
                                                        [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[0]}]

# connected via PLL (Normal Mode, Divided by 2)
create_generated_clock -name pll_1_clk_1        -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \
                                                -divide_by 2   [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[1]}]

# connected via PLL (Normal Mode, Divided by 4)
create_generated_clock -name pll_1_clk_2        -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \
                                                -divide_by 4   [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[2]}]

# connected via PLL (Normal Mode, -3ns phase shift
create_generated_clock -name pll_1_clk_3        -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \
                                                -phase -54.000 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[3]}]

create_generated_clock -name clock_dram         -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[3]}] \
                                                        [get_ports {dram_clk_o}]


#**************************************************************
# Set Clock Groups
#**************************************************************

# EPCS16N-98364 (EPCS): cut all paths between the write and read clock (just one of both is active at any time)
set_clock_groups -asynchronous -group [get_clocks epcs_wd_clk] -group [get_clocks epcs_rd_clk] -group [get_clocks {pll_1_clk_0}]

# JTAG: cut all paths to and from tck
#set_clock_groups -asynchronous -group [get_clocks tck]


#**************************************************************
# Set Clock Latency
#**************************************************************


#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -from { pll_1_clk_0 }         -to { pll_1_clk_0 } 0.2
set_clock_uncertainty -from { pll_1_clk_0 }         -to { pll_1_clk_1 } 0.2
set_clock_uncertainty -from { pll_1_clk_0 }         -to { clock_dram } 0.2

set_clock_uncertainty -from { pll_1_clk_1 }         -to { pll_1_clk_1 } 0.2
set_clock_uncertainty -from { pll_1_clk_1 }         -to { pll_1_clk_0 } 0.2

set_clock_uncertainty -from { pll_1_clk_2 }         -to { pll_1_clk_2 } 0.2
set_clock_uncertainty -from { pll_1_clk_2 }         -to { pll_1_clk_0 } 0.2

set_clock_uncertainty -from { et_phy_clk }          -to { pll_1_clk_0 } 0.2

set_clock_uncertainty -from { clock_dram }          -to { clock_dram } 0.2
set_clock_uncertainty -from { clock_dram }          -to { pll_1_clk_0 } 0.2

set_clock_uncertainty -from { clock_ssram }         -to { pll_1_clk_0 } 0.2

#**************************************************************
# Set Input Delay
#**************************************************************

# SDRAM Timing Constraints IS42S16800D-7TL
#-------------------
# CAS Latency (Latency = 3), Access Time From CLK: t_AC  = 6.5 ns
set_input_delay -max -clock [get_clocks {clock_dram}] 6.500  [get_ports {dram_d_io[*]}]
# CAS Latency (Latency = 3), Output Data Hold Time: t_OH  = 2.7 ns
set_input_delay -min -clock [get_clocks {clock_dram}] 2.700  [get_ports {dram_d_io[*]}]

# EPCS16N-98364 (EPCS)
#-------------------
# Read Operation Timing, Clock Falling Edge to Data: t_nCLK2D = 15 ns (FROM FALLING CLOCK EDGE)
set_input_delay -max -clock_fall -clock epcs_rd_clk  15.000 [get_ports {config_data0_i}]
# Read Operation Timing, Output Hold time is not known, therfore we chosse 0 ns (FROM FALLING CLOCK EDGE)
set_input_delay -min -clock_fall -clock epcs_rd_clk  0.000  [get_ports {config_data0_i}]

# JTAG: constrain the TDI and TMS port [Quartus II TimeQuest Timing Analyzer Cookbook]
#-------------------------------------------------------------------------------------
#set_input_delay -clock tck 20 \
#  [get_ports altera_reserved_tdi]
#set_input_delay -clock tck 20 \
#  [get_ports altera_reserved_tms]

#**************************************************************
# Set Output Delay
#**************************************************************

# SDRAM Timing Constraints IS42S16800D-7TL
#-------------------
# Address/Input Data/CKE/COMMAND Setup Time: t_AS, t_DS, t_CKS, t_CS = 1.5 ns
set_output_delay  -max -clock [get_clocks {clock_dram}] 1.500  [get_ports {dram_a_o[*] dram_d_io[*] \
                                                                dram_cke_o dram_ba?_n_o dram_cs_n_o \
                                                                dram_ras_n_o dram_cas_n_o dram_we_n_o dram_ldqm_o dram_udqm_o}]
# Address/Input Data/CKE/COMMAND Hold Time: t_AH, t_DH, t_CKH, t_CH = 0.8 ns
set_output_delay  -min -clock [get_clocks {clock_dram}] -0.800  [get_ports {dram_a_o[*] dram_d_io[*] \
                                                                dram_cke_o dram_ba?_n_o dram_cs_n_o \
                                                                dram_ras_n_o dram_cas_n_o dram_we_n_o dram_ldqm_o dram_udqm_o}]

# EPCS16N-98364 (EPCS)
#-------------------
# Write Operation Timing, Data In Setup time: t_DSU = 5 ns
set_output_delay -max -clock epcs_wd_clk 5.000 [get_ports config_asd0_o]
# Write Operation Timing, Data In Hold time: t_DH = 5 ns
set_output_delay -min -clock epcs_wd_clk -5.000 [get_ports config_asd0_o]

# Write Operation Timing, Chip select Setup time: t_NCSSU = 10 ns
set_output_delay -max -clock epcs_wd_clk 10.000 [get_ports config_ce_n_o]

# Write Operation Timing, Chip select Hold time: t_NCSH = 10 ns
set_output_delay -min -clock epcs_wd_clk -10.000 [get_ports config_ce_n_o]

# JTAG: constrain the TDO port [Quartus II TimeQuest Timing Analyzer Cookbook]
#-----------------------------------------------------------------------------
#set_output_delay -clock tck 20 \
#  [get_ports altera_reserved_tdo]

#**************************************************************
# Set False Path
#**************************************************************

# Main input reset
#-------------------
set_false_path -from [get_ports {fpga_reset_n_i}]

# NIOS CPU
#-------------------
# Nios uart signals (RS232)
set_false_path -from [get_ports {nios_uart_rxd_i}]
set_false_path -to   [get_ports {nios_uart_txd_o}]

# GP-LEDs
#-------------------
set_false_path -to   [get_ports {gp_led_o[*] gen_led_g_o[*] gen_led_r_o[*]}]

# Switch Input
#-------------------
set_false_path -from [get_ports {switch_i[*]}]

# Reserve Pins
#-------------------
set_false_path -from [get_ports {reserve?_i}]

# Philips ISP 1362 OTG Controller
# timing is to do in SOPC System
# -------------------
set_false_path -from [get_ports {otg_d_io[*] otg_int0_i otg_int1_i otg_dreq0_i otg_dreq1_i usb_clk_i}]
set_false_path -to   [get_ports {otg_d_io[*] otg_a_o[*] otg_cs_n_o otg_oe_n_o otg_we_n_o otg_reset_n_o otg_dack0_n_o otg_dack1_n_o}]

# Parallel Flash (S29AL032D 70TF100)
# timing is to do in SOPC System
#-------------------
set_false_path -from [get_ports {flash_d_io[*]}]
set_false_path -to   [get_ports {flash_d_io[*] flash_a_o[*] flash_we_n_o flash_reset_n_o flash_oe_n_o flash_ce_n_o fash_acc_o}]

#**************************************************************
# Set Multicycle Path
#**************************************************************

# compensate the negative phase shift of the output SDRAM clock for hold check
# clock_50           ___|----|____|----|
# clock_dram_pll     __|----|____|----|
# Compensate setup path from clock_50 to clock_dram_pll
set_multicycle_path -from [get_clocks pll_1_clk_0] \
                    -to [get_clocks clock_dram] \
                    -setup -end 1

# Compensate hold path from clock_dram_pll to clock_50 (default sdc configuration)
set_multicycle_path -from [get_clocks pll_1_clk_0] \
                    -to [get_clocks clock_dram] \
                    -hold -start 0

# clock_dram_pll     __|----|____|----|
# clock_50           ___|----|____|----|
# Compensate setup path from clock_dram_pll to clock_50
set_multicycle_path -from [get_clocks clock_dram] \
                    -to [get_clocks pll_1_clk_0] \
                    -setup -start 2

# Hold is already correct and has not to be defined

#set_multicycle_path -from [get_clocks {clock_50}] \
#                    -to [get_fanouts [get_registers {clk_50_en}]] \
#                    -hold -end 1

#**************************************************************
# Set Input Transition
#**************************************************************


#**************************************************************
# Set Load
#**************************************************************