path: root/quartus/dionysos_sinet.qsf

set_global_assignment -name TOP_LEVEL_ENTITY dionysos_top
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors.  Please refer to the
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		sinet_su_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.

# Set preflow scripts
# ===================
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:dionysos_version_number.tcl"

# Project-Wide Assignments
# ========================
set_global_assignment -name LAST_QUARTUS_VERSION 8.0
set_global_assignment -name INCREMENTAL_COMPILATION OFF



# Clock inputs
# --------------
set_location_assignment PIN_G2 -to clock_50_i
set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i
set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i
set_location_assignment PIN_G21 -to usb_clk_i
set_location_assignment PIN_G22 -to sdfe_clk_20mhz_i
set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i
set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i
set_location_assignment PIN_A12 -to aux_clk_n_i
set_location_assignment PIN_B12 -to aux_clk_p_i
set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i
set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i
set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i
set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i

# FPGA programming pins
# ---------------------
set_location_assignment PIN_E2 -to config_ce_n_o
set_location_assignment PIN_D1 -to config_asd0_o
set_location_assignment PIN_K1 -to config_data0_i
set_location_assignment PIN_K2 -to config_dclk_o

# FPGA bank 1
# -------------
set_location_assignment PIN_G4 -to nios_uart_txd_o
set_location_assignment PIN_B2 -to nios_uart_rxd_i
set_location_assignment PIN_G3 -to mstt_uart_txd_o
set_location_assignment PIN_B1 -to mstt_uart_rxd_i
set_location_assignment PIN_G5 -to gen_led_r_o[5]
set_location_assignment PIN_E4 -to gen_led_g_o[5]
set_location_assignment PIN_E3 -to iom_du_o
set_location_assignment PIN_C2 -to iom_dd_i
set_location_assignment PIN_C1 -to iom_fsc_o
set_location_assignment PIN_D2 -to iom_dclk_o
set_location_assignment PIN_H7 -to reserve0_i
set_location_assignment PIN_J6 -to reserve1_i
set_location_assignment PIN_E1 -to i2c_sda_io
set_location_assignment PIN_F2 -to i2c_scl_o
set_location_assignment PIN_F1 -to gen_led_r_o[4]
set_location_assignment PIN_H8 -to gen_led_g_o[4]
set_location_assignment PIN_J5 -to switch_i[0]
set_location_assignment PIN_H5 -to switch_i[1]
set_location_assignment PIN_L8 -to switch_i[2]
set_location_assignment PIN_K8 -to switch_i[3]
set_location_assignment PIN_K7 -to gen_led_r_o[0]
set_location_assignment PIN_J4 -to gen_led_g_o[0]
set_location_assignment PIN_H2 -to gp_led_o[0]
set_location_assignment PIN_H1 -to gp_led_o[1]
set_location_assignment PIN_J3 -to gp_led_o[2]
set_location_assignment PIN_J2 -to gp_led_o[3]

# FPGA bank 2
# -------------                  
set_location_assignment PIN_L6 -to ssram_d_io[2]
set_location_assignment PIN_M6 -to ssram_a_o[17]
set_location_assignment PIN_M2 -to ssram_bwc_n_o
set_location_assignment PIN_M1 -to ssram_bwb_n_o
set_location_assignment PIN_M4 -to ssram_ce_n_o
set_location_assignment PIN_M3 -to ssram_bwd_n_o
set_location_assignment PIN_N2 -to ssram_a_o[14]
set_location_assignment PIN_N1 -to ssram_a_o[13]
set_location_assignment PIN_L7 -to ssram_d_io[3]
set_location_assignment PIN_M5 -to ssram_a_o[16]
set_location_assignment PIN_P2 -to ssram_d_io[12]
set_location_assignment PIN_P1 -to ssram_d_io[11]
set_location_assignment PIN_R2 -to ssram_a_o[12]
set_location_assignment PIN_R1 -to ssram_a_o[11]
set_location_assignment PIN_N5 -to ssram_a_o[15]
set_location_assignment PIN_P4 -to ssram_d_io[14]
set_location_assignment PIN_P3 -to ssram_d_io[13]
set_location_assignment PIN_U2 -to ssram_a_o[6]
set_location_assignment PIN_U1 -to ssram_a_o[0]
set_location_assignment PIN_V2 -to ssram_a_o[4]
set_location_assignment PIN_V1 -to ssram_a_o[3]
set_location_assignment PIN_P5 -to ssram_d_io[15]
set_location_assignment PIN_N6 -to ssram_oe_n_o
set_location_assignment PIN_M7 -to ssram_d_io[0]
set_location_assignment PIN_M8 -to ssram_d_io[1]
set_location_assignment PIN_N8 -to ssram_bwa_n_o
set_location_assignment PIN_W2 -to ssram_a_o[2]
set_location_assignment PIN_W1 -to ssram_d_io[16]
set_location_assignment PIN_Y2 -to ssram_d_io[7]
set_location_assignment PIN_Y1 -to ssram_d_io[6]
set_location_assignment PIN_T3 -to ssram_a_o[7]
set_location_assignment PIN_N7 -to ssram_we_n_o
set_location_assignment PIN_P7 -to ssram_a_o[18]
set_location_assignment PIN_AA2 -to ssram_d_io[5]
set_location_assignment PIN_AA1 -to ssram_d_io[4]
set_location_assignment PIN_V4 -to ssram_a_o[1]
set_location_assignment PIN_V3 -to ssram_a_o[5]
set_location_assignment PIN_P6 -to ssram_d_io[17]
set_location_assignment PIN_T5 -to ssram_a_o[9]
set_location_assignment PIN_T4 -to ssram_a_o[8]
set_location_assignment PIN_R5 -to ssram_d_io[8]
set_location_assignment PIN_R6 -to ssram_d_io[9]
set_location_assignment PIN_R7 -to ssram_d_io[10]
set_location_assignment PIN_T7 -to ssram_a_o[10]

# FPGA bank 3
# -------------
set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i
set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i
set_location_assignment PIN_U8 -to et_phy1_crs_1_i
set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0]
set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1]
set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2]
set_location_assignment PIN_AA3 -to ssram_clk_o
set_location_assignment PIN_AB3 -to reserve7_i
set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3]
set_location_assignment PIN_V7 -to et_phy1_col_1_i
set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o
set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0]
set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1]
set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2]
set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3]
set_location_assignment PIN_W7 -to et_phy1_int_1_i
set_location_assignment PIN_Y7 -to reserve2_i
set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i
set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i
set_location_assignment PIN_W8 -to et_phy1_crs_2_i
set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0]
set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1]
set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2]
set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3]
set_location_assignment PIN_T11 -to et_phy1_col_2_i
set_location_assignment PIN_V9 -to reserve3_i
set_location_assignment PIN_V10 -to et_phy1_tx_en_2_o
set_location_assignment PIN_U10 -to et_phy1_txd_2_o[0]
set_location_assignment PIN_AA8 -to et_phy1_txd_2_o[1]
set_location_assignment PIN_AB8 -to et_phy1_txd_2_o[2]
set_location_assignment PIN_AA9 -to et_phy1_txd_2_o[3]
set_location_assignment PIN_AB9 -to et_phy1_int_2_i
set_location_assignment PIN_U11 -to et_phy1_mdc_o
set_location_assignment PIN_V11 -to et_phy1_mdio_io
set_location_assignment PIN_W10 -to rst_et_phy1_n_o
set_location_assignment PIN_Y10 -to gen_led_r_o[3]
set_location_assignment PIN_AA10 -to gen_led_g_o[3]
                                 
# FPGA bank 4           
# -------------           
set_location_assignment PIN_AA13 -to otg_d_io[0]
set_location_assignment PIN_AB13 -to otg_d_io[1]
set_location_assignment PIN_AA14 -to otg_d_io[2]
set_location_assignment PIN_AB14 -to otg_d_io[3]
set_location_assignment PIN_V12 -to otg_d_io[4]
set_location_assignment PIN_W13 -to otg_d_io[5]
set_location_assignment PIN_Y13 -to otg_d_io[6]
set_location_assignment PIN_AA15 -to otg_d_io[7]
set_location_assignment PIN_AB15 -to otg_d_io[8]
set_location_assignment PIN_U12 -to otg_d_io[9]
set_location_assignment PIN_AA16 -to otg_d_io[10]
set_location_assignment PIN_AB16 -to otg_d_io[11]
set_location_assignment PIN_T12 -to otg_d_io[12]
set_location_assignment PIN_T13 -to otg_d_io[13]
set_location_assignment PIN_V13 -to otg_d_io[14]
set_location_assignment PIN_W14 -to otg_d_io[15]
set_location_assignment PIN_U13 -to otg_a_o[0]
set_location_assignment PIN_V14 -to otg_a_o[1]
set_location_assignment PIN_U14 -to otg_cs_n_o
set_location_assignment PIN_U15 -to otg_we_n_o
set_location_assignment PIN_V15 -to otg_oe_n_o
set_location_assignment PIN_W15 -to otg_int0_i
set_location_assignment PIN_T14 -to otg_int1_i
set_location_assignment PIN_T15 -to otg_reset_n_o
set_location_assignment PIN_AB18 -to otg_dreq0_i
set_location_assignment PIN_AA17 -to otg_dreq1_i
set_location_assignment PIN_AB17 -to otg_dack0_n_o
set_location_assignment PIN_AA18 -to otg_dack1_n_o
set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i
set_location_assignment PIN_W17 -to gen_led_r_o[6]
set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o
set_location_assignment PIN_AB20 -to gen_led_r_o[2]
set_location_assignment PIN_V16 -to gen_led_g_o[2]
set_location_assignment PIN_U16 -to reserve4_i
set_location_assignment PIN_U17 -to reserve5_i
set_location_assignment PIN_T16 -to aux_clk_p_o
set_location_assignment PIN_R16 -to aux_clk_n_o
set_location_assignment PIN_R15 -to gen_led_g_o[6]
 
# FPGA bank 5          
# -------------        
set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3]
set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2]
set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1]
set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0]
set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3]
set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2]
set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1]
set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0]
set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3]
set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2]
set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1]
set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0]
set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3]
set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2]
set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1]
set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0]
set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i
set_location_assignment PIN_V21 -to et_phy2_crs_2_i
set_location_assignment PIN_R20 -to rst_et_phy2_n_o
set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i
set_location_assignment PIN_U21 -to et_phy2_col_2_i
set_location_assignment PIN_R18 -to et_phy2_crs_1_i
set_location_assignment PIN_R19 -to et_phy2_col_1_i
set_location_assignment PIN_N16 -to mpd_io[0]
set_location_assignment PIN_R22 -to mpd_io[1]
set_location_assignment PIN_R21 -to mpd_io[2]
set_location_assignment PIN_P20 -to mpd_io[3]
set_location_assignment PIN_P22 -to mpd_io[4]
set_location_assignment PIN_P21 -to mpd_io[5]
set_location_assignment PIN_N20 -to mpd_io[6]
set_location_assignment PIN_N19 -to mpd_io[7]
set_location_assignment PIN_N18 -to reserve6_i
set_location_assignment PIN_N21 -to fpga_reset_n_i
set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i
set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o
set_location_assignment PIN_AA20 -to et_phy2_int_1_i
set_location_assignment PIN_M20 -to et_phy2_int_2_i
set_location_assignment PIN_M19 -to et_phy2_mdc_o
set_location_assignment PIN_M16 -to et_phy2_mdio_io
set_global_assignment -name DEVICE EP3C40F484C6

# FPGA bank 6
# -------------          
set_location_assignment PIN_L22 -to flash_a_o[2]
set_location_assignment PIN_L21 -to flash_a_o[4]
set_location_assignment PIN_K19 -to fash_acc_o
set_location_assignment PIN_K22 -to flash_a_o[6]
set_location_assignment PIN_K21 -to flash_a_o[18]
set_location_assignment PIN_J22 -to flash_a_o[12]
set_location_assignment PIN_J21 -to flash_a_o[14]
set_location_assignment PIN_H22 -to flash_a_o[13]
set_location_assignment PIN_H21 -to flash_a_o[11]
set_location_assignment PIN_K17 -to flash_a_o[9]
set_location_assignment PIN_K18 -to flash_we_n_o
set_location_assignment PIN_J18 -to flash_a_o[16]
set_location_assignment PIN_F22 -to flash_oe_n_o
set_location_assignment PIN_F21 -to flash_d_io[1]
set_location_assignment PIN_H20 -to flash_a_o[8]
set_location_assignment PIN_H19 -to flash_reset_n_o
set_location_assignment PIN_E22 -to flash_a_o[10]
set_location_assignment PIN_E21 -to flash_a_o[20]
set_location_assignment PIN_H18 -to flash_a_o[7]
set_location_assignment PIN_J17 -to flash_a_o[15]
set_location_assignment PIN_H16 -to flash_a_o[3]
set_location_assignment PIN_D22 -to flash_a_o[17]
set_location_assignment PIN_D21 -to flash_a_o[19]
set_location_assignment PIN_F20 -to flash_d_io[3]
set_location_assignment PIN_F19 -to flash_d_io[4]
set_location_assignment PIN_G18 -to flash_a_o[1]
set_location_assignment PIN_H17 -to flash_a_o[5]
set_location_assignment PIN_C22 -to flash_d_io[5]
set_location_assignment PIN_C21 -to flash_a_o[21]
set_location_assignment PIN_B22 -to flash_d_io[0]
set_location_assignment PIN_B21 -to flash_a_o[0]
set_location_assignment PIN_C20 -to flash_d_io[2]
set_location_assignment PIN_D20 -to flash_d_io[7]
set_location_assignment PIN_F17 -to flash_d_io[6]
set_location_assignment PIN_G17 -to flash_ce_n_o

# FPGA bank 7                             
# -------------
set_location_assignment PIN_F16 -to dram_a_o[0]
set_location_assignment PIN_E16 -to dram_a_o[1]
set_location_assignment PIN_F15 -to dram_a_o[2]
set_location_assignment PIN_G16 -to dram_a_o[3]
set_location_assignment PIN_G15 -to dram_a_o[4]
set_location_assignment PIN_F14 -to dram_a_o[5]
set_location_assignment PIN_H15 -to dram_a_o[6]
set_location_assignment PIN_H14 -to dram_a_o[7]
set_location_assignment PIN_D17 -to dram_a_o[8]
set_location_assignment PIN_C19 -to dram_a_o[9]
set_location_assignment PIN_D19 -to dram_a_o[10]
set_location_assignment PIN_A20 -to dram_a_o[11]
set_location_assignment PIN_B20 -to dram_clk_o
set_location_assignment PIN_C17 -to dram_d_io[0]
set_location_assignment PIN_B19 -to dram_d_io[1]
set_location_assignment PIN_A19 -to dram_d_io[2]
set_location_assignment PIN_A18 -to dram_d_io[3]
set_location_assignment PIN_B18 -to dram_d_io[4]
set_location_assignment PIN_D15 -to dram_d_io[5]
set_location_assignment PIN_E15 -to dram_d_io[6]
set_location_assignment PIN_G14 -to dram_d_io[7]
set_location_assignment PIN_G13 -to dram_d_io[8]
set_location_assignment PIN_A17 -to dram_d_io[9]
set_location_assignment PIN_B17 -to dram_d_io[10]
set_location_assignment PIN_A16 -to dram_d_io[11]
set_location_assignment PIN_B16 -to dram_d_io[12]
set_location_assignment PIN_C15 -to dram_d_io[13]
set_location_assignment PIN_E14 -to dram_d_io[14]
set_location_assignment PIN_F13 -to dram_d_io[15]
set_location_assignment PIN_B15 -to dram_cke_o
set_location_assignment PIN_C13 -to dram_ldqm_o
set_location_assignment PIN_D13 -to dram_udqm_o
set_location_assignment PIN_E13 -to dram_we_n_o
set_location_assignment PIN_A14 -to dram_cas_n_o
set_location_assignment PIN_B14 -to dram_ras_n_o
set_location_assignment PIN_A13 -to dram_cs_n_o
set_location_assignment PIN_B13 -to dram_ba0_n_o
set_location_assignment PIN_E12 -to dram_ba1_n_o
set_location_assignment PIN_F11 -to dram_a_o[12]

# FPGA bank 8
# -------------
set_location_assignment PIN_D10 -to sdfe_dout_0_i
set_location_assignment PIN_E10 -to sdfe_din_0_o
set_location_assignment PIN_A10 -to sdfe_aux_0_0_o
set_location_assignment PIN_B10 -to sdfe_aux_0_1_o
set_location_assignment PIN_A9 -to sdfe_aux_0_2_o
set_location_assignment PIN_B9 -to sdfe_aux_0_3_i
set_location_assignment PIN_C10 -to sdfe_aux_0_4_i
set_location_assignment PIN_G11 -to sdfe_aux_0_5_i
set_location_assignment PIN_A8 -to sdfe_refclk_0_i
set_location_assignment PIN_B8 -to reserve8_i
set_location_assignment PIN_B7 -to sdfe_dout_3_i
set_location_assignment PIN_A6 -to sdfe_din_3_o
set_location_assignment PIN_B6 -to sdfe_aux_3_0_o
set_location_assignment PIN_E9 -to sdfe_aux_3_1_o
set_location_assignment PIN_C8 -to sdfe_aux_3_2_o
set_location_assignment PIN_C7 -to sdfe_aux_3_3_i
set_location_assignment PIN_H11 -to sdfe_aux_3_4_i
set_location_assignment PIN_H10 -to sdfe_aux_3_5_i
set_location_assignment PIN_A5 -to sdfe_refclk_3_i
set_location_assignment PIN_B5 -to gen_led_r_o[1]
set_location_assignment PIN_G10 -to gen_led_g_o[1]
set_location_assignment PIN_F10 -to sdfe_scdi_o
set_location_assignment PIN_C6 -to sdfe_scdo_i
set_location_assignment PIN_D7 -to sdfe_scck_o
set_location_assignment PIN_A4 -to rst_sdfe_n_o
set_location_assignment PIN_B4 -to mprdy_n_io
set_location_assignment PIN_F8 -to mpcs_n_o
set_location_assignment PIN_G8 -to mpwr_n_o
set_location_assignment PIN_A3 -to mprd_n_o
set_location_assignment PIN_B3 -to mpint_n_i
set_location_assignment PIN_D6 -to mpclk_o
set_location_assignment PIN_E7 -to isdn_cs_n_o
set_location_assignment PIN_C3 -to mpad_o[0]
set_location_assignment PIN_C4 -to mpad_o[1]
set_location_assignment PIN_F7 -to mpad_o[2]
set_location_assignment PIN_G7 -to mpad_o[3]
set_location_assignment PIN_F9 -to mpad_o[4]
set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o




# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"

# Assembler Assignments
# =====================


set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to mdio_io



#SOURCES
#-------
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to et_phy2_tx_clk_2_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_reset_n_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_sdfe_n_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_0_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_1_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_2_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_3_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_4_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_5_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_0_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_1_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_2_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_3_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_4_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_5_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_din_0_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_din_3_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_dout_0_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_dout_3_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_refclk_0_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_refclk_3_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scck_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scdi_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scdo_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reserve8_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpint_n_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mprd_n_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mprdy_n_io
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpwr_n_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to isdn_cs_n_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpclk_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpcs_n_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_r_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_g_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to et_phy_clk_50mhz_o
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[8]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[9]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[10]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[11]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[12]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[13]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[14]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[15]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[16]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[17]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 25 OHM WITHOUT CALIBRATION" -to ssram_clk_o
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE su_debug.stp
set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name QIP_FILE ../../../lib/altera/sinet_pll.qip
set_global_assignment -name VHDL_FILE ../../../lib/altera/sinet_pll.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/sinet_filter.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/prp_filter.vhd
set_global_assignment -name VHDL_FILE ../../../lib/learning_table/ip_request_to_learningtable.vhd
set_global_assignment -name VHDL_FILE ../../../lib/learning_table/address_comparator.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/arp_filter.vhd
set_global_assignment -name VHDL_FILE descriptor_memory.vhd
set_global_assignment -name VHDL_FILE sgdma_rx.vhd
set_global_assignment -name VHDL_FILE sgdma_tx.vhd
set_global_assignment -name VHDL_FILE ISP1362.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/rmii_phy_to_mii_mac.vhd
set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su_ucom_generic_globals.vhd
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/edge_det.vhd
set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/pwm_unit.vhd
set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/led_controller.vhd
set_global_assignment -name VHDL_FILE ../../../lib/learning_table/sinet_types.vhd
set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learning_table.vhd
set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learningtable_mng.vhd
set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learningtable_ram_mng.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_rx_mux.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/dp_ram_intern.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_core_top.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo_read_mng.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo_write_mng.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_filter.vhd
set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_generic_globals.vhd
set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/ucom/dsl_port_switch.vhd
set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/ucom/ucom_generic_top.vhd
set_global_assignment -name VHDL_FILE firmware_id_pkg.vhd
set_global_assignment -name SDC_FILE dionysos_sinet.sdc
set_global_assignment -name QIP_FILE nios_1.qip
set_global_assignment -name VHDL_FILE ../../../lib/bus/avalon/dm9000a_if.vhd
set_global_assignment -name VHDL_FILE nios_1_burst_3.vhd
set_global_assignment -name VHDL_FILE nios_1_burst_1.vhd
set_global_assignment -name VHDL_FILE nios_1_burst_2.vhd
set_global_assignment -name VHDL_FILE nios_1_burst_0.vhd
set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_sysclk.vhd -library work
set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_tck.vhd -library work
set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_wrapper.vhd -library work
set_global_assignment -name VHDL_FILE cpu_0_mult_cell.vhd -library work
set_global_assignment -name VHDL_FILE cpu_0_test_bench.vhd -library work
set_global_assignment -name VHDL_FILE cpu_0.vhd -library work
set_global_assignment -name VHDL_FILE epcs_controller.vhd -library work
set_global_assignment -name VHDL_FILE nios_16bit_interface_wbd_1.vhd -library work
set_global_assignment -name VHDL_FILE nios_1.vhd -library work
set_global_assignment -name VHDL_FILE nios_interrupt_quirk_hdcl_rx.vhd -library work
set_global_assignment -name VHDL_FILE nios_interrupt_quirk_hdlc_tx.vhd -library work
set_global_assignment -name VHDL_FILE nios_interrupt_quirk_mac.vhd -library work
set_global_assignment -name VHDL_FILE sdram_0_test_component.vhd -library work
set_global_assignment -name VHDL_FILE sdram_0.vhd -library work
set_global_assignment -name VHDL_FILE sysid.vhd -library work
set_global_assignment -name VHDL_FILE timer_0.vhd -library work
set_global_assignment -name VHDL_FILE timer_1.vhd -library work
set_global_assignment -name VHDL_FILE uart_0.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/pck_crc16_d8.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/ribu.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx_crc.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx_buffer.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx_crc.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx_buffer.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/hdlc_avalon_if.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/phy_init_top.vhd -library hdlc
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/uart.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/ccitt_crc_generator.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/communication_register.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_read_dfe_to_su.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_read_su_to_dfe.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_write_dfe_to_su.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_write_su_to_dfe.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/ethernet_header_plus.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/frame_analyzer.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/framerasen_generator.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/priority_mux.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/rahmen_minus.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/rahmen_plus.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/sequence_number_crc_generator.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/sicherungs_fsm.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/access_mux.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dfe_connector_top.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/misc/reduce_pkg.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/misc/ines_vhdl_lib_base_pkg.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/register_r.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/buf_sync.vhd
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/register_rw.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/bibuf_async.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/bibuf_sync.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/reset_sync.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/generic_sp_ram.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/misc/components/ram.vhd -library ines_misc
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/clock_logic.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/pkg_rt_nrt_segment.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_arbit.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_flag_det.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_ser_par.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_arbit.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_flag_data_mux.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_par_ser.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rt_nrt_segment_top.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/clk_edge_det.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_top.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_top.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/bus/wishbone/wb_register_rw.vhd -library ines_bus
set_global_assignment -name VHDL_FILE ../../../lib/bus/avalon/avalon_multimaster_16.vhd -library ines_bus
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/ethernet_pkg.vhd -library ines_ethernet
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/prp_rct_detect.vhd -library ines_ethernet
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/crc_generator.vhd -library ines_ethernet
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/rmii_in_out.vhd -library ines_ethernet
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mii_management_transmit.vhd -library ines_ethernet
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mdio_interface.vhd -library ines_ethernet
set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mac_filter.vhd -library ines_ethernet
set_global_assignment -name VHDL_FILE ../../../lib/altera/hash_ram_112.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/altera/mac_table_96.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/arbiter_pkg.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/ram_arbiter_sram.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/ram_arbiter_ssram.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_core_register_mapping.vhd
set_global_assignment -name VHDL_FILE ../../../lib/su_core/traffic_led_delay.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/learn_stw_addr.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/counter_32.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/counters.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/cpu_interface.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_queue.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_fifo.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_fifo.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/hash_lookup.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/seq_count_ram.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/seq_counter.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_serializer.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_filter_rules.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/mac_addr_comparator.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_mac_filter.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_processing12.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_processing3.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_processing.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_core.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/region_global.vhd
set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su/su_generic_top.vhd -library work
set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su_ucom_generic_top.vhd -library work
set_global_assignment -name VHDL_FILE ../dionysos_top.vhd
set_global_assignment -name SIGNALTAP_FILE tx_serializer.stp
set_global_assignment -name SIGNALTAP_FILE su_input_ports.stp
set_global_assignment -name SIGNALTAP_FILE su_input_ports_neuer_su_core_und_neuer_hdlc_.stp
set_global_assignment -name SIGNALTAP_FILE su_input_ports_lange_frames_und_wenig_segmente.stp
set_global_assignment -name SIGNALTAP_FILE rmii_phy_to_mii_mac_debug.stp
set_global_assignment -name SIGNALTAP_FILE rmii_phy_to_mii_mac_debug_2.stp
set_global_assignment -name SIGNALTAP_FILE tse_mac_debug.stp
set_global_assignment -name SIGNALTAP_FILE tsgdma_debug.stp
set_global_assignment -name SIGNALTAP_FILE tse_mag_debug.stp
set_global_assignment -name SIGNALTAP_FILE su_debug.stp
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON