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author | Scott Wood <oss@buserror.net> | 2016-10-17 13:42:23 -0500 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-11-01 17:26:15 -0700 |
commit | 7c1c5413a7bdf1c9adc8d979521f1b8286366aef (patch) | |
tree | 91e4786a854b7b2b1372d7e427436f2006e008b0 /Documentation/devicetree/bindings | |
parent | c7129375312732f006ba9054c12ae4d4097d5519 (diff) |
clk: qoriq: Don't allow CPU clocks higher than starting value
The boot-time frequency of a CPU is considered its rated maximum, as we
have no other source of such information. However, this was previously
only used for chips with 80% restrictions on secondary PLLs. This
usually wasn't a problem because most chips/configs boot with a divider
of /1, with other dividers being used only for dynamic frequency
reduction. However, at least one config (LS1021A at less than 1 GHz)
uses a different divider for top speed. This was causing cpufreq to set
a frequency beyond the chip's rated speed.
This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs,
similar to the existing 80% limit that only applied to some.
Signed-off-by: Scott Wood <oss@buserror.net>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
0 files changed, 0 insertions, 0 deletions