summaryrefslogtreecommitdiff
path: root/include/net/ethoc.h
diff options
context:
space:
mode:
authorSinclair Yeh <syeh@vmware.com>2017-01-18 14:14:01 -0800
committerSinclair Yeh <syeh@vmware.com>2017-01-26 19:53:34 -0800
commit242ef5d483594a2bed6b8a2685849c83e7810d17 (patch)
tree7ed12099198823ccb1d41180be6b85cee5ecce3f /include/net/ethoc.h
parent54a07c7bb0da0343734c78212bbe9f3735394962 (diff)
drm/vmwgfx: Fix depth input into drm_mode_legacy_fb_format
Currently the pitch is passed in as depth. This causes drm_mode_legacy_fb_format() to return the wrong pixel format. The wrong pixel format will be rejected by vmw_kms_new_framebuffer(), thus leaving par->set_fb to NULL. This eventually causes a crash in vmw_fb_setcolreg() when the code tries to dereference par->set_fb. Signed-off-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Diffstat (limited to 'include/net/ethoc.h')
0 files changed, 0 insertions, 0 deletions
bits (interrupt mask) went out of sync with the *enum* declaring the EESR bits (interrupt status) WRT bit naming and formatting. I'd like to restore the consistency by using EESIPR as the bit name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the bits according to the available Renesas SH77{34|63} manuals; additionally, reconstruct couple names using the EESR bit declaration above... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/pmu-events/arch/powerpc/power8/cache.json')