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authorSaeed Mahameed <saeedm@mellanox.com>2016-12-06 13:53:49 +0200
committerSaeed Mahameed <saeedm@mellanox.com>2017-02-06 18:20:17 +0200
commita6f402e4990145252ce4fde59b273fa7e4f91e1b (patch)
treee9629cd82413793b5a8c12d736cdeaa44f4e16cc /include/net/netns/hash.h
parent2b31f7ae5f645edd852addfca445895b5806f3f9 (diff)
net/mlx5e: Tx, no inline copy on ConnectX-5
ConnectX-5 and later HW generations will report min inline mode == MLX5_INLINE_MODE_NONE, which means driver is not required to copy packet headers to inline fields of TX WQE. When inline is not required, vlan insertion will be handled in the TX descriptor rather than copy to inline. For LSO case driver is still required to copy headers, for the HW to duplicate on wire. This will improve CPU utilization and boost TX performance. Tested with pktgen burst single flow: CPU: Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz HCA: Mellanox Technologies MT28800 Family [ConnectX-5 Ex] Before: 15.1Mpps After: 17.2Mpps Improvement: 14% Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Diffstat (limited to 'include/net/netns/hash.h')
0 files changed, 0 insertions, 0 deletions
ts: Narrow down Entry Size when used as a divider irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility irqchip/gic-v3: Use nops macro for Cavium ThunderX erratum 23154 irqchip/gic-v3: Convert arm64 GIC accessors to {read,write}_sysreg_s genirq/msi: Drop artificial PCI dependency irqchip/bcm7038-l1: Implement irq_cpu_offline() callback genirq/affinity: Use default affinity mask for reserved vectors genirq/affinity: Take reserved vectors into account when spreading irqs PCI: Remove the irq_affinity mask from struct pci_dev ...
Diffstat (limited to 'include/net/caif')