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authorMichael Chan <michael.chan@broadcom.com>2017-02-06 16:55:37 -0500
committerDavid S. Miller <davem@davemloft.net>2017-02-07 13:30:59 -0500
commit4e5dbbda4c40a239e2ed4bbc98f2aa320e4dcca2 (patch)
tree2a8c4e105ea6af6d289372e9277a2100d995ac2c /include/uapi/xen
parentc61fb99cae51958a9096d8540c8c05e74cfa7e59 (diff)
bnxt_en: Use event bit map in RX path.
In the current code, we have separate rx_event and agg_event parameters to keep track of rx and aggregation events. Combine these events into an u8 event mask with different bits defined for different events. This way, it is easier to expand the logic to include XDP tx events. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/uapi/xen')
0 files changed, 0 insertions, 0 deletions
posing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/dt-bindings/leds')