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authorFlorian Fainelli <f.fainelli@gmail.com>2017-02-06 13:01:16 -0800
committerDavid S. Miller <davem@davemloft.net>2017-02-07 13:03:10 -0500
commitb08d46b01e995dd7b653b22d35bd1d958d6ee9b4 (patch)
treed62db18848a1d901434f01223cd9bcca6683ceab /net/ipv6/ip6_fib.c
parent8d1fb01df8f64af14c833805dcbd05bf4582e028 (diff)
net: phy: bcm7xxx: Add BCM74371 PHY ID
Add the BCM74371 PHY ID to the list of supported chips. This is a 28nm technology Gigabit PHY SoC. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/ipv6/ip6_fib.c')
0 files changed, 0 insertions, 0 deletions
ecause it has already happened on CPU0 and we don't find a newer microcode revision on CPU1. Which doesn't set the intel_ucode_patch pointer and at initrd jettisoning time we don't save the microcode patch for later application. Now, when we suspend to RAM, the loaded microcode gets cleared so we need to reload but there's no patch saved in the cache. Removing the optimization fixes this issue and all is fine and dandy. Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/trace/events/context_tracking.h')