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authorDeepak Khungar <deepak.khungar@broadcom.com>2017-02-12 19:18:18 -0500
committerDavid S. Miller <davem@davemloft.net>2017-02-12 22:18:49 -0500
commit32b40798c1b40343641f04cdfd09652af70ea0e9 (patch)
tree9d14df9b9731493be45194bc9360de8812cb3f91 /net/irda/irda_device.c
parentb451c8b69e70de299aa6061e1fa6afbb4d7c1f9e (diff)
bnxt_en: Added PCI IDs for BCM57452 and BCM57454 ASICs
Signed-off-by: Deepak Khungar <deepak.khungar@broadcom.com> Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/irda/irda_device.c')
0 files changed, 0 insertions, 0 deletions
AP had already done that but it can also hurt us: Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for example) which updates the microcode on the BSP but since the microcode engine is shared between the two threads, the update on CPU1 doesn't happen because it has already happened on CPU0 and we don't find a newer microcode revision on CPU1. Which doesn't set the intel_ucode_patch pointer and at initrd jettisoning time we don't save the microcode patch for later application. Now, when we suspend to RAM, the loaded microcode gets cleared so we need to reload but there's no patch saved in the cache. Removing the optimization fixes this issue and all is fine and dandy. Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'sound/soc/codecs/cs42l42.c')