summaryrefslogtreecommitdiff
path: root/net/llc/llc_s_ac.c
diff options
context:
space:
mode:
authorMarc Kleine-Budde <mkl@pengutronix.de>2015-08-31 21:03:29 +0200
committerMarc Kleine-Budde <mkl@pengutronix.de>2017-02-06 15:13:41 +0100
commit4bd888a80b1d48dbd83f1cbf806e923a30051958 (patch)
tree088e2fbfb38f81a35399fc8e5b1226c56cc4db90 /net/llc/llc_s_ac.c
parent30164759db1bb1062bdf0f92451f57ed295cfa48 (diff)
can: flexcan: activate individual RX masking and initialize reg_rximr
Modern flexcan IP cores support two RX modes. One is using the 6 fames deep hardware FIFO, the other is using up to 64 mailboxes (in non FIFO mode). For now only the HW FIFO mode is activated. In order to make use of the RX mailboxes the individual RX masking feature has to be activated, otherwise matching mailboxes are overwritten during the reception process. This however switches on the individual RX masking, which uses reg_rximr registers for masking. This patch activates the individual RX masking feature unconditionally and initializes the mask registers (reg_rximr) with 0x0 == "don't care", which switches off any filtering. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'net/llc/llc_s_ac.c')
0 files changed, 0 insertions, 0 deletions
intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/drm/drm_displayid.h')