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authorMichael Chan <michael.chan@broadcom.com>2017-02-12 19:18:12 -0500
committerDavid S. Miller <davem@davemloft.net>2017-02-12 22:18:49 -0500
commita79a5276aa2f844bd368c1d3d5a625e1fbefd989 (patch)
treea8db414709298ea3018f2a121a9bf8c201d0882b /net/rxrpc/local_object.c
parentcb4d1d6261453677feb54e7a09c23fc7648dd6bc (diff)
bnxt_en: Fix ethtool -l pre-set max combined channel.
With commit d1e7925e6d80 ("bnxt_en: Centralize logic to reserve rings."), ring allocation for combined rings has become stricter. A combined ring must now have an rx-tx ring pair. The pre-set max. for combined rings should now be min(rx, tx). Fixes: d1e7925e6d80 ("bnxt_en: Centralize logic to reserve rings.") Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/rxrpc/local_object.c')
0 files changed, 0 insertions, 0 deletions
require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'sound/firewire/fireworks/Makefile')