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authorJiri Pirko <jiri@mellanox.com>2017-02-03 10:28:51 +0100
committerDavid S. Miller <davem@davemloft.net>2017-02-03 16:35:37 -0500
commit2946fde9fd7f6c38beaaf581514b706d07c7aec0 (patch)
treee49f64c1463a1941715aaa6e7e2392d97733ccd8 /sound/soc/intel/skylake/skl-sst-dsp.c
parent3d67576da15167b2669e4765ca9e383f6bcb4171 (diff)
mlxsw: item: Add 8bit item helpers
Item heplers for 8bit values are needed, let's add them. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'sound/soc/intel/skylake/skl-sst-dsp.c')
0 files changed, 0 insertions, 0 deletions
so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'net/batman-adv/multicast.h')