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path: root/drivers/usb/serial/cypress_m8.h
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#ifndef CYPRESS_M8_H
#define CYPRESS_M8_H

/*
 * definitions and function prototypes used for the cypress USB to Serial
 * controller
 */

/*
 * For sending our feature buffer - controlling serial communication states.
 * Linux HID has no support for serial devices so we do this through the driver
 */
#define HID_REQ_GET_REPORT	0x01
#define HID_REQ_SET_REPORT	0x09

/* List other cypress USB to Serial devices here, and add them to the id_table */

/* DeLorme Earthmate USB - a GPS device */
#define VENDOR_ID_DELORME		0x1163
#define PRODUCT_ID_EARTHMATEUSB		0x0100
#define PRODUCT_ID_EARTHMATEUSB_LT20	0x0200

/* Cypress HID->COM RS232 Adapter */
#define VENDOR_ID_CYPRESS		0x04b4
#define PRODUCT_ID_CYPHIDCOM		0x5500

/* FRWD Dongle - a GPS sports watch */
#define VENDOR_ID_FRWD			0x6737
#define PRODUCT_ID_CYPHIDCOM_FRWD	0x0001

/* Powercom UPS, chip CY7C63723 */
#define VENDOR_ID_POWERCOM		0x0d9f
#define PRODUCT_ID_UPS			0x0002

/* Nokia CA-42 USB to serial cable */
#define VENDOR_ID_DAZZLE		0x07d0
#define PRODUCT_ID_CA42			0x4101
/* End of device listing */

/* Used for setting / requesting serial line settings */
#define CYPRESS_SET_CONFIG	0x01
#define CYPRESS_GET_CONFIG	0x02

/* Used for throttle control */
#define THROTTLED		0x1
#define ACTUALLY_THROTTLED	0x2

/*
 * chiptypes - used in case firmware differs from the generic form ... offering
 * different baud speeds/etc.
 */
#define CT_EARTHMATE	0x01
#define CT_CYPHIDCOM	0x02
#define CT_CA42V2	0x03
#define CT_GENERIC	0x0F
/* End of chiptype definitions */

/*
 * RS-232 serial data communication protocol definitions.
 *
 * These are sent / read at byte 0 of the input/output hid reports.
 * You can find these values defined in the CY4601 USB to Serial design notes.
 */

#define CONTROL_DTR	0x20	/* data terminal ready */
#define CONTROL_RTS	0x10	/* request to send */
#define CONTROL_RESET	0x08	/* sent with output report */

#define UART_MSR_MASK	0xf0
#define UART_RI		0x80	/* ring indicator */
#define UART_CD		0x40	/* carrier detect */
#define UART_DSR	0x20	/* data set ready */
#define UART_CTS	0x10	/* clear to send */
#define CYP_ERROR	0x08	/* received from input report */

/* End of RS-232 protocol definitions */

#endif /* CYPRESS_M8_H */
0x14/0x2c) .. .. [ 240.664311] INFO: task partprobe:564 blocked for more than 120 seconds. [ 240.670943] Not tainted 4.1.13-00510-g9d91424 #2 [ 240.676078] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 240.683922] partprobe D c047504c 0 564 486 0x00000000 [ 240.690318] [<c047504c>] (__schedule) from [<c04754a0>] (schedule+0x40/0x98) [ 240.697396] [<c04754a0>] (schedule) from [<c0477d40>] (schedule_timeout+0x148/0x188) [ 240.705149] [<c0477d40>] (schedule_timeout) from [<c0476040>] (wait_for_common+0xa4/0x170) [ 240.713446] [<c0476040>] (wait_for_common) from [<c01f3300>] (submit_bio_wait+0x58/0x64) [ 240.721571] [<c01f3300>] (submit_bio_wait) from [<c01fbbd8>] (blkdev_issue_flush+0x60/0x88) [ 240.729957] [<c01fbbd8>] (blkdev_issue_flush) from [<c010ff84>] (blkdev_fsync+0x34/0x44) [ 240.738083] [<c010ff84>] (blkdev_fsync) from [<c0109594>] (do_fsync+0x3c/0x64) [ 240.745319] [<c0109594>] (do_fsync) from [<c000ffc0>] (ret_fast_syscall+0x0/0x3c) .. Here is the detailed sequence showing when this issue may happen: 1) At probe time, mmci device is initialized and card busy detection based on DAT[0] monitoring is enabled. 2) Later during run time, since card reported to support internal caches, a MMCI_SWITCH command is sent to eMMC device with FLUSH_CACHE operation. On receiving this command, eMMC may enter busy state (for a relatively short time in the case of the dead-lock). 3) Then mmci interrupt is raised and mmci_irq() is called: MMCISTATUS register is read and is equal to 0x01000440. So the following status bits are set: - MCI_CMDRESPEND (= 6) - MCI_DATABLOCKEND (= 10) - MCI_ST_CARDBUSY (= 24) Since MMCIMASK0 register is 0x3FF, status variable is set to 0x00000040 and BIT MCI_CMDRESPEND is cleared by writing MMCICLEAR register. Then mmci_cmd_irq() is called. Considering the following conditions: - host->busy_status is 0, - this is a "busy response", - reading again MMCISTATUS register gives 0x1000400, MMCIMASK0 is updated to unmask MCI_ST_BUSYEND bit. Thus, MMCIMASK0 is set to 0x010003FF and host->busy_status is set to wait for busy end completion. Back again in status loop of mmci_irq(), we quickly go through mmci_data_irq() as there are no data in that case. And we finally go through following test at the end of while(status) loop: /* * Don't poll for busy completion in irq context. */ if (host->variant->busy_detect && host->busy_status) status &= ~host->variant->busy_detect_flag; Because status variable is not yet null (is equal to 0x40), we do not leave interrupt context yet but we loop again into while(status) loop. So we run across following steps: a) MMCISTATUS register is read again and this time is equal to 0x01000400. So that following bits are set: - MCI_DATABLOCKEND (= 10) - MCI_ST_CARDBUSY (= 24) Since MMCIMASK0 register is equal to 0x010003FF: b) status variable is set to 0x01000000. c) MCI_ST_CARDBUSY bit is cleared by writing MMCICLEAR register. Then, mmci_cmd_irq() is called one more time. Since host->busy_status is set and that MCI_ST_CARDBUSY is set in status variable, we just return from this function. Back again in mmci_irq(), status variable is set to 0 and we finally leave the while(status) loop. As a result we leave interrupt context, waiting for busy end interrupt event. Now, consider that busy end completion is raised IN BETWEEN steps 3.a) and 3.c). In such a case, we may mistakenly clear busy end interrupt at step 3.c) while it has not yet been processed. This will result in mmc command to wait forever for a busy end completion that will never happen. To fix the problem, this patch implements the following changes: Considering that the mmci seems to be triggering the IRQ on both edges while monitoring DAT0 for busy completion and that same status bit is used to monitor start and end of busy detection, special care must be taken to make sure that both start and end interrupts are always cleared one after the other. 1) Clearing of card busy bit is moved in mmc_cmd_irq() function where unmasking of busy end bit is effectively handled. 2) Just before unmasking busy end event, busy start event is cleared by writing card busy bit in MMCICLEAR register. 3) Finally, once we are no more busy with a command, busy end event is cleared writing again card busy bit in MMCICLEAR register. This patch has been tested with the ST Accordo5 machine, not yet supported upstream but relies on the mmci driver. Signed-off-by: Sarang Mairal <sarang.mairal@garmin.com> Signed-off-by: Jean-Nicolas Graux <jean-nicolas.graux@st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/usb/chipidea/otg.h')