pid: fix lockdep deadlock warning due to ucount_lock

=========================================================
[ INFO: possible irq lock inversion dependency detected ]
4.10.0-rc2-00024-g4aecec9-dirty #118 Tainted: G        W
---------------------------------------------------------
swapper/1/0 just changed the state of lock:
 (&(&sighand->siglock)->rlock){-.....}, at: [<ffffffffbd0a1bc6>] __lock_task_sighand+0xb6/0x2c0
but this lock took another, HARDIRQ-unsafe lock in the past:
 (ucounts_lock){+.+...}
and interrupts could create inverse lock ordering between them.
other info that might help us debug this:
Chain exists of:                 &(&sighand->siglock)->rlock --> &(&tty->ctrl_lock)->rlock --> ucounts_lock
 Possible interrupt unsafe locking scenario:
       CPU0                    CPU1
       ----                    ----
  lock(ucounts_lock);
                               local_irq_disable();
                               lock(&(&sighand->siglock)->rlock);
                               lock(&(&tty->ctrl_lock)->rlock);
  <Interrupt>
    lock(&(&sighand->siglock)->rlock);

 *** DEADLOCK ***

This patch removes a dependency between rlock and ucount_lock.

Fixes: f333c700c610 ("pidns: Add a limit on the number of pid namespaces")
Cc: stable@vger.kernel.org
Signed-off-by: Andrei Vagin <avagin@openvz.org>
Acked-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>

path: root/include/dt-bindings/clock/imx1-clock.h

/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __DT_BINDINGS_CLOCK_IMX1_H
#define __DT_BINDINGS_CLOCK_IMX1_H

#define IMX1_CLK_DUMMY		0
#define IMX1_CLK_CLK32		1
#define IMX1_CLK_CLK16M_EXT	2
#define IMX1_CLK_CLK16M		3
#define IMX1_CLK_CLK32_PREMULT	4
#define IMX1_CLK_PREM		5
#define IMX1_CLK_MPLL		6
#define IMX1_CLK_MPLL_GATE	7
#define IMX1_CLK_SPLL		8
#define IMX1_CLK_SPLL_GATE	9
#define IMX1_CLK_MCU		10
#define IMX1_CLK_FCLK		11
#define IMX1_CLK_HCLK		12
#define IMX1_CLK_CLK48M		13
#define IMX1_CLK_PER1		14
#define IMX1_CLK_PER2		15
#define IMX1_CLK_PER3		16
#define IMX1_CLK_CLKO		17
#define IMX1_CLK_UART3_GATE	18
#define IMX1_CLK_SSI2_GATE	19
#define IMX1_CLK_BROM_GATE	20
#define IMX1_CLK_DMA_GATE	21
#define IMX1_CLK_CSI_GATE	22
#define IMX1_CLK_MMA_GATE	23
#define IMX1_CLK_USBD_GATE	24
#define IMX1_CLK_MAX		25

#endif