PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies

In a struct pcie_link_state, link->root points to the pcie_link_state of
the root of the PCIe hierarchy.  For the topmost link, this points to
itself (link->root = link).  For others, we copy the pointer from the
parent (link->root = link->parent->root).

Previously we recognized that Root Ports originated PCIe hierarchies, but
we treated PCI/PCI-X to PCIe Bridges as being in the middle of the
hierarchy, and when we tried to copy the pointer from link->parent->root,
there was no parent, and we dereferenced a NULL pointer:

  BUG: unable to handle kernel NULL pointer dereference at 0000000000000090
  IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820

Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just
like Root Ports do, so link->root for these devices should also point to
itself.

Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411
Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181
Tested-by: lists@ssl-mail.com
Tested-by: Jayachandran C. <jnair@caviumnetworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v4.2+

path: root/include/dt-bindings/clock/maxim,max77802.h

/*
 * Copyright (C) 2014 Google, Inc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Device Tree binding constants clocks for the Maxim 77802 PMIC.
 */

#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H

/* Fixed rate clocks. */

#define MAX77802_CLK_32K_AP		0
#define MAX77802_CLK_32K_CP		1

/* Total number of clocks. */
#define MAX77802_CLKS_NUM		(MAX77802_CLK_32K_CP + 1)

#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */