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path: root/include/dt-bindings/clock/r8a7743-cpg-mssr.h
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/*
 * Copyright (C) 2016 Cogent Embedded Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r8a7743 CPG Core Clocks */
#define R8A7743_CLK_Z		0
#define R8A7743_CLK_ZG		1
#define R8A7743_CLK_ZTR		2
#define R8A7743_CLK_ZTRD2	3
#define R8A7743_CLK_ZT		4
#define R8A7743_CLK_ZX		5
#define R8A7743_CLK_ZS		6
#define R8A7743_CLK_HP		7
#define R8A7743_CLK_B		9
#define R8A7743_CLK_LB		10
#define R8A7743_CLK_P		11
#define R8A7743_CLK_CL		12
#define R8A7743_CLK_M2		13
#define R8A7743_CLK_ZB3		15
#define R8A7743_CLK_ZB3D2	16
#define R8A7743_CLK_DDR		17
#define R8A7743_CLK_SDH		18
#define R8A7743_CLK_SD0		19
#define R8A7743_CLK_SD2		20
#define R8A7743_CLK_SD3		21
#define R8A7743_CLK_MMC0	22
#define R8A7743_CLK_MP		23
#define R8A7743_CLK_QSPI	26
#define R8A7743_CLK_CP		27
#define R8A7743_CLK_RCAN	28
#define R8A7743_CLK_R		29
#define R8A7743_CLK_OSC		30

#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */
af90d3dd1&id2=1b89970d81bbd52720fc64a3fe9572ee33588363'>diff)
pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler
According to VLI64 Intel Atom E3800 Specification Update (#329901) concurrent read accesses may result in returning 0xffffffff and write accesses may be dropped silently. To workaround all accesses must be protected by locks. Cc: stable@vger.kernel.org Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/lib/traceevent/event-utils.h')