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/*
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef __SOC_TEGRA_AHB_H__
#define __SOC_TEGRA_AHB_H__

extern int tegra_ahb_enable_smmu(struct device_node *ahb);

#endif /* __SOC_TEGRA_AHB_H__ */
nfo' class='commit-info'> authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2017-01-29 15:07:34 +0300 committerDavid S. Miller <davem@davemloft.net>2017-01-30 22:05:43 -0500 commit1a0bee6c1e788218fd1d141db320db970aace7f0 (patch) tree46c4116bc8ef4a7df718516a648597d9e21c15f1 /tools/thermal/tmon/README parent63c190429020a9701b42887ac22c28f287f1762f (diff)
sh_eth: rename EESIPR bits
Since the commit b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth") the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with the *enum* declaring the EESR bits (interrupt status) WRT bit naming and formatting. I'd like to restore the consistency by using EESIPR as the bit name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the bits according to the available Renesas SH77{34|63} manuals; additionally, reconstruct couple names using the EESR bit declaration above... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/thermal/tmon/README')