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/*
 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
 *		      http://www.simtec.co.uk/products/SWLINUX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * S3C2410 IIS register definition
*/

#ifndef __SAMSUNG_REGS_IIS_H__
#define __SAMSUNG_REGS_IIS_H__

#define S3C2410_IISCON			(0x00)

#define S3C2410_IISCON_LRINDEX		(1 << 8)
#define S3C2410_IISCON_TXFIFORDY	(1 << 7)
#define S3C2410_IISCON_RXFIFORDY	(1 << 6)
#define S3C2410_IISCON_TXDMAEN		(1 << 5)
#define S3C2410_IISCON_RXDMAEN		(1 << 4)
#define S3C2410_IISCON_TXIDLE		(1 << 3)
#define S3C2410_IISCON_RXIDLE		(1 << 2)
#define S3C2410_IISCON_PSCEN		(1 << 1)
#define S3C2410_IISCON_IISEN		(1 << 0)

#define S3C2410_IISMOD			(0x04)

#define S3C2440_IISMOD_MPLL		(1 << 9)
#define S3C2410_IISMOD_SLAVE		(1 << 8)
#define S3C2410_IISMOD_NOXFER		(0 << 6)
#define S3C2410_IISMOD_RXMODE		(1 << 6)
#define S3C2410_IISMOD_TXMODE		(2 << 6)
#define S3C2410_IISMOD_TXRXMODE		(3 << 6)
#define S3C2410_IISMOD_LR_LLOW		(0 << 5)
#define S3C2410_IISMOD_LR_RLOW		(1 << 5)
#define S3C2410_IISMOD_IIS		(0 << 4)
#define S3C2410_IISMOD_MSB		(1 << 4)
#define S3C2410_IISMOD_8BIT		(0 << 3)
#define S3C2410_IISMOD_16BIT		(1 << 3)
#define S3C2410_IISMOD_BITMASK		(1 << 3)
#define S3C2410_IISMOD_256FS		(0 << 2)
#define S3C2410_IISMOD_384FS		(1 << 2)
#define S3C2410_IISMOD_16FS		(0 << 0)
#define S3C2410_IISMOD_32FS		(1 << 0)
#define S3C2410_IISMOD_48FS		(2 << 0)
#define S3C2410_IISMOD_FS_MASK		(3 << 0)

#define S3C2410_IISPSR			(0x08)

#define S3C2410_IISPSR_INTMASK		(31 << 5)
#define S3C2410_IISPSR_INTSHIFT		(5)
#define S3C2410_IISPSR_EXTMASK		(31 << 0)
#define S3C2410_IISPSR_EXTSHFIT		(0)

#define S3C2410_IISFCON			(0x0c)

#define S3C2410_IISFCON_TXDMA		(1 << 15)
#define S3C2410_IISFCON_RXDMA		(1 << 14)
#define S3C2410_IISFCON_TXENABLE	(1 << 13)
#define S3C2410_IISFCON_RXENABLE	(1 << 12)
#define S3C2410_IISFCON_TXMASK		(0x3f << 6)
#define S3C2410_IISFCON_TXSHIFT		(6)
#define S3C2410_IISFCON_RXMASK		(0x3f)
#define S3C2410_IISFCON_RXSHIFT		(0)

#define S3C2410_IISFIFO			(0x10)

#endif /* __SAMSUNG_REGS_IIS_H__ */
ead+0xdc/0xf4) [ 240.365339] [<c003cf90>] (kthread) from [<c0010068>] (ret_from_fork+0x14/0x2c) .. .. [ 240.664311] INFO: task partprobe:564 blocked for more than 120 seconds. [ 240.670943] Not tainted 4.1.13-00510-g9d91424 #2 [ 240.676078] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 240.683922] partprobe D c047504c 0 564 486 0x00000000 [ 240.690318] [<c047504c>] (__schedule) from [<c04754a0>] (schedule+0x40/0x98) [ 240.697396] [<c04754a0>] (schedule) from [<c0477d40>] (schedule_timeout+0x148/0x188) [ 240.705149] [<c0477d40>] (schedule_timeout) from [<c0476040>] (wait_for_common+0xa4/0x170) [ 240.713446] [<c0476040>] (wait_for_common) from [<c01f3300>] (submit_bio_wait+0x58/0x64) [ 240.721571] [<c01f3300>] (submit_bio_wait) from [<c01fbbd8>] (blkdev_issue_flush+0x60/0x88) [ 240.729957] [<c01fbbd8>] (blkdev_issue_flush) from [<c010ff84>] (blkdev_fsync+0x34/0x44) [ 240.738083] [<c010ff84>] (blkdev_fsync) from [<c0109594>] (do_fsync+0x3c/0x64) [ 240.745319] [<c0109594>] (do_fsync) from [<c000ffc0>] (ret_fast_syscall+0x0/0x3c) .. Here is the detailed sequence showing when this issue may happen: 1) At probe time, mmci device is initialized and card busy detection based on DAT[0] monitoring is enabled. 2) Later during run time, since card reported to support internal caches, a MMCI_SWITCH command is sent to eMMC device with FLUSH_CACHE operation. On receiving this command, eMMC may enter busy state (for a relatively short time in the case of the dead-lock). 3) Then mmci interrupt is raised and mmci_irq() is called: MMCISTATUS register is read and is equal to 0x01000440. So the following status bits are set: - MCI_CMDRESPEND (= 6) - MCI_DATABLOCKEND (= 10) - MCI_ST_CARDBUSY (= 24) Since MMCIMASK0 register is 0x3FF, status variable is set to 0x00000040 and BIT MCI_CMDRESPEND is cleared by writing MMCICLEAR register. Then mmci_cmd_irq() is called. Considering the following conditions: - host->busy_status is 0, - this is a "busy response", - reading again MMCISTATUS register gives 0x1000400, MMCIMASK0 is updated to unmask MCI_ST_BUSYEND bit. Thus, MMCIMASK0 is set to 0x010003FF and host->busy_status is set to wait for busy end completion. Back again in status loop of mmci_irq(), we quickly go through mmci_data_irq() as there are no data in that case. And we finally go through following test at the end of while(status) loop: /* * Don't poll for busy completion in irq context. */ if (host->variant->busy_detect && host->busy_status) status &= ~host->variant->busy_detect_flag; Because status variable is not yet null (is equal to 0x40), we do not leave interrupt context yet but we loop again into while(status) loop. So we run across following steps: a) MMCISTATUS register is read again and this time is equal to 0x01000400. So that following bits are set: - MCI_DATABLOCKEND (= 10) - MCI_ST_CARDBUSY (= 24) Since MMCIMASK0 register is equal to 0x010003FF: b) status variable is set to 0x01000000. c) MCI_ST_CARDBUSY bit is cleared by writing MMCICLEAR register. Then, mmci_cmd_irq() is called one more time. Since host->busy_status is set and that MCI_ST_CARDBUSY is set in status variable, we just return from this function. Back again in mmci_irq(), status variable is set to 0 and we finally leave the while(status) loop. As a result we leave interrupt context, waiting for busy end interrupt event. Now, consider that busy end completion is raised IN BETWEEN steps 3.a) and 3.c). In such a case, we may mistakenly clear busy end interrupt at step 3.c) while it has not yet been processed. This will result in mmc command to wait forever for a busy end completion that will never happen. To fix the problem, this patch implements the following changes: Considering that the mmci seems to be triggering the IRQ on both edges while monitoring DAT0 for busy completion and that same status bit is used to monitor start and end of busy detection, special care must be taken to make sure that both start and end interrupts are always cleared one after the other. 1) Clearing of card busy bit is moved in mmc_cmd_irq() function where unmasking of busy end bit is effectively handled. 2) Just before unmasking busy end event, busy start event is cleared by writing card busy bit in MMCICLEAR register. 3) Finally, once we are no more busy with a command, busy end event is cleared writing again card busy bit in MMCICLEAR register. This patch has been tested with the ST Accordo5 machine, not yet supported upstream but relies on the mmci driver. Signed-off-by: Sarang Mairal <sarang.mairal@garmin.com> Signed-off-by: Jean-Nicolas Graux <jean-nicolas.graux@st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/usb/musb/Makefile')