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path: root/tools/perf/arch/x86/tests/regs_load.S
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#include <linux/linkage.h>

#define AX	 0
#define BX	 1 * 8
#define CX	 2 * 8
#define DX	 3 * 8
#define SI	 4 * 8
#define DI	 5 * 8
#define BP	 6 * 8
#define SP	 7 * 8
#define IP	 8 * 8
#define FLAGS	 9 * 8
#define CS	10 * 8
#define SS	11 * 8
#define DS	12 * 8
#define ES	13 * 8
#define FS	14 * 8
#define GS	15 * 8
#define R8	16 * 8
#define R9	17 * 8
#define R10	18 * 8
#define R11	19 * 8
#define R12	20 * 8
#define R13	21 * 8
#define R14	22 * 8
#define R15	23 * 8

.text
#ifdef HAVE_ARCH_X86_64_SUPPORT
ENTRY(perf_regs_load)
	movq %rax, AX(%rdi)
	movq %rbx, BX(%rdi)
	movq %rcx, CX(%rdi)
	movq %rdx, DX(%rdi)
	movq %rsi, SI(%rdi)
	movq %rdi, DI(%rdi)
	movq %rbp, BP(%rdi)

	leaq 8(%rsp), %rax /* exclude this call.  */
	movq %rax, SP(%rdi)

	movq 0(%rsp), %rax
	movq %rax, IP(%rdi)

	movq $0, FLAGS(%rdi)
	movq $0, CS(%rdi)
	movq $0, SS(%rdi)
	movq $0, DS(%rdi)
	movq $0, ES(%rdi)
	movq $0, FS(%rdi)
	movq $0, GS(%rdi)

	movq %r8,  R8(%rdi)
	movq %r9,  R9(%rdi)
	movq %r10, R10(%rdi)
	movq %r11, R11(%rdi)
	movq %r12, R12(%rdi)
	movq %r13, R13(%rdi)
	movq %r14, R14(%rdi)
	movq %r15, R15(%rdi)
	ret
ENDPROC(perf_regs_load)
#else
ENTRY(perf_regs_load)
	push %edi
	movl 8(%esp), %edi
	movl %eax, AX(%edi)
	movl %ebx, BX(%edi)
	movl %ecx, CX(%edi)
	movl %edx, DX(%edi)
	movl %esi, SI(%edi)
	pop %eax
	movl %eax, DI(%edi)
	movl %ebp, BP(%edi)

	leal 4(%esp), %eax /* exclude this call.  */
	movl %eax, SP(%edi)

	movl 0(%esp), %eax
	movl %eax, IP(%edi)

	movl $0, FLAGS(%edi)
	movl $0, CS(%edi)
	movl $0, SS(%edi)
	movl $0, DS(%edi)
	movl $0, ES(%edi)
	movl $0, FS(%edi)
	movl $0, GS(%edi)
	ret
ENDPROC(perf_regs_load)
#endif

/*
 * We need to provide note.GNU-stack section, saying that we want
 * NOT executable stack. Otherwise the final linking will assume that
 * the ELF stack should not be restricted at all and set it RWX.
 */
.section .note.GNU-stack,"",@progbits
;c0476040>] (wait_for_common+0xa4/0x170) [ 240.713446] [<c0476040>] (wait_for_common) from [<c01f3300>] (submit_bio_wait+0x58/0x64) [ 240.721571] [<c01f3300>] (submit_bio_wait) from [<c01fbbd8>] (blkdev_issue_flush+0x60/0x88) [ 240.729957] [<c01fbbd8>] (blkdev_issue_flush) from [<c010ff84>] (blkdev_fsync+0x34/0x44) [ 240.738083] [<c010ff84>] (blkdev_fsync) from [<c0109594>] (do_fsync+0x3c/0x64) [ 240.745319] [<c0109594>] (do_fsync) from [<c000ffc0>] (ret_fast_syscall+0x0/0x3c) .. Here is the detailed sequence showing when this issue may happen: 1) At probe time, mmci device is initialized and card busy detection based on DAT[0] monitoring is enabled. 2) Later during run time, since card reported to support internal caches, a MMCI_SWITCH command is sent to eMMC device with FLUSH_CACHE operation. On receiving this command, eMMC may enter busy state (for a relatively short time in the case of the dead-lock). 3) Then mmci interrupt is raised and mmci_irq() is called: MMCISTATUS register is read and is equal to 0x01000440. So the following status bits are set: - MCI_CMDRESPEND (= 6) - MCI_DATABLOCKEND (= 10) - MCI_ST_CARDBUSY (= 24) Since MMCIMASK0 register is 0x3FF, status variable is set to 0x00000040 and BIT MCI_CMDRESPEND is cleared by writing MMCICLEAR register. Then mmci_cmd_irq() is called. Considering the following conditions: - host->busy_status is 0, - this is a "busy response", - reading again MMCISTATUS register gives 0x1000400, MMCIMASK0 is updated to unmask MCI_ST_BUSYEND bit. Thus, MMCIMASK0 is set to 0x010003FF and host->busy_status is set to wait for busy end completion. Back again in status loop of mmci_irq(), we quickly go through mmci_data_irq() as there are no data in that case. And we finally go through following test at the end of while(status) loop: /* * Don't poll for busy completion in irq context. */ if (host->variant->busy_detect && host->busy_status) status &= ~host->variant->busy_detect_flag; Because status variable is not yet null (is equal to 0x40), we do not leave interrupt context yet but we loop again into while(status) loop. So we run across following steps: a) MMCISTATUS register is read again and this time is equal to 0x01000400. So that following bits are set: - MCI_DATABLOCKEND (= 10) - MCI_ST_CARDBUSY (= 24) Since MMCIMASK0 register is equal to 0x010003FF: b) status variable is set to 0x01000000. c) MCI_ST_CARDBUSY bit is cleared by writing MMCICLEAR register. Then, mmci_cmd_irq() is called one more time. Since host->busy_status is set and that MCI_ST_CARDBUSY is set in status variable, we just return from this function. Back again in mmci_irq(), status variable is set to 0 and we finally leave the while(status) loop. As a result we leave interrupt context, waiting for busy end interrupt event. Now, consider that busy end completion is raised IN BETWEEN steps 3.a) and 3.c). In such a case, we may mistakenly clear busy end interrupt at step 3.c) while it has not yet been processed. This will result in mmc command to wait forever for a busy end completion that will never happen. To fix the problem, this patch implements the following changes: Considering that the mmci seems to be triggering the IRQ on both edges while monitoring DAT0 for busy completion and that same status bit is used to monitor start and end of busy detection, special care must be taken to make sure that both start and end interrupts are always cleared one after the other. 1) Clearing of card busy bit is moved in mmc_cmd_irq() function where unmasking of busy end bit is effectively handled. 2) Just before unmasking busy end event, busy start event is cleared by writing card busy bit in MMCICLEAR register. 3) Finally, once we are no more busy with a command, busy end event is cleared writing again card busy bit in MMCICLEAR register. This patch has been tested with the ST Accordo5 machine, not yet supported upstream but relies on the mmci driver. Signed-off-by: Sarang Mairal <sarang.mairal@garmin.com> Signed-off-by: Jean-Nicolas Graux <jean-nicolas.graux@st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/usb/atm/speedtch.c')