PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller

Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP.

[bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap
error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix]
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>

path: root/colorize.h

#ifndef COLORIZE_H
#define COLORIZE_H

#define colorize_start(fore)		"\033[" __##fore "m"
#define colorize_start_full(fore, back)	"\033[" __##fore ";" __on_##back "m"
#define colorize_end()			"\033[" __reset "m"

#endif /* COLORIZE_H */