Updates all over the place (mostly devices)HEADmaster

1 files changed, 146 insertions, 161 deletions

diff --git a/timer.c b/timer.c
index b468f9b..198f672 100644
--- a/timer.c
+++ b/timer.c
@@ -1,215 +1,200 @@
 /*
-    Nios-sim - one simple NIOSII simulator only for personal interest and fun.
-    Copyright (C) 2010  chysun2000@gmail.com
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License along
-    with this program; if not, write to the Free Software Foundation, Inc.,
-    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-*/
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2010 chysun2000@gmail.com
+ *
+ * This file is part of nios2sim-ng.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
 
 #include <stdio.h>
+#include <stdlib.h>
 #include <string.h>
 
-#include "public.h"
+#include "nios2sim-ng.h"
+#include "device.h"
 #include "timer.h"
-#include "niosii.h"
 
+struct timer {
+	struct io_register regs[TIMER_REG_COUNT];
+	uint32_t set_period;
+	uint32_t curr_count;
+};
 
-static struct timer_hw hw;
-static uint32_t valid_mask[TIMER_REG_CNT] = {
-	0x3,0xF,0xFFFF,0xFFFF,0xFFFF,0xFFFF
+static const uint32_t timer_valid_mask[TIMER_REG_COUNT] = {
+	0x3, 0xF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF
 };
 
-static uint32_t only_read_mask[TIMER_REG_CNT] = {
-	0x2,0,0,0,0,0
+static const uint32_t timer_read_only_mask[TIMER_REG_COUNT] = {
+	0x2, 0, 0, 0, 0, 0
 };
 
-static void update_period_reg(void);
-static void timer_init(struct io_device * self)
+static int timer_init(struct device *dev)
 {
-	int32_t i = 0;
-	
-	self->priv_data = &hw;
-	
-	for (i=0;i<TIMER_REG_CNT;i++){
-		hw.io_regs[i].addr = TIMER_BASE_ADDR + 4 * i;
-		hw.io_regs[i].value = 0;
-		hw.io_regs[i].valid_mask = valid_mask[i];
-		hw.io_regs[i].only_read_mask = only_read_mask[i];
+	unsigned int i;
+	struct timer *t = malloc(sizeof(struct timer));
+	struct io_register *regs;
+
+	if (unlikely(t == NULL))
+		return -1;
+
+	/* Initialite registers */
+	regs = t->regs;
+	for (i = 0; i < TIMER_REG_COUNT; i++) {
+		io_register_init(&regs[i],
+				 TIMER_BASE + REG_TO_OFF(i),
+				 timer_valid_mask[i],
+				 timer_read_only_mask[i],
+				 0);
 	}
-	
-	hw.set_period = 0;
-	hw.curr_count = 0;
 
-	printf("Timer Core at 0x%08X-0x%08X\n", hw.io_regs[0].addr, 
-		   hw.io_regs[TIMER_REG_CNT-1].addr);
+	t->set_period = 0;
+	t->curr_count = 0;
+	dev->priv = t;
+
+	return 0;
 }
 
-static int timer_is_belong(uint32_t address)
+static void update_period_reg(struct timer *t)
 {
-	int32_t ret_val = ADDR_IS_NOT_DEV;
-	if ((address >= TIMER_BASE_ADDR) && (address < (TIMER_BASE_ADDR + TIMER_REG_CNT * 4))){
-		ret_val = ADDR_IS_DEV;
-	}
+	t->regs[TIMER_PERIODL_REG].value = t->curr_count & 0xFFFF;
+	t->regs[TIMER_PERIODH_REG].value = (t->curr_count & 0xFFFF0000) >> 16;
+	//copy_snapshot();
+}
 
-	return ret_val;
+#if 0
+static void copy_snapshot(struct timer *t)
+{
+	t->regs[TIMER_SNAPL_REG].value = t->regs[TIMER_PERIODL_REG].value;
+	t->regs[TIMER_SNAPH_REG].value = t->regs[TIMER_PERIODH_REG].value;
 }
-static void copy_snapshot(void);
-static uint32_t timer_read(struct io_device * self, uint32_t addr, uint32_t data_len)
+
+static uint32_t timer_read(struct device *dev, uint32_t addr, uint32_t data_len)
 {
+	struct timer *t = dev->priv;
 	uint32_t ret_val = 0;
 	uint32_t index = 0;
-	
-	index = (addr - TIMER_BASE_ADDR) / 4;
-	if (index >= 0 && index < TIMER_REG_CNT){
-		if (index == TIM_REG_SNAPL || index == TIM_REG_SNAPH){
-			copy_snapshot();
-		}
-		ret_val = hw.io_regs[index].value & hw.io_regs[index].valid_mask;
-		ret_val = io_read_data(ret_val, data_len);
-	}
+
+	index = (addr - dev->base) / 4;
+	if (index >= TIMER_REG_COUNT)
+		return 0;
+
+	if (index == TIMER_SNAPL_REG || index == TIMER_SNAPH_REG)
+		copy_snapshot(t);
+	ret_val = io_register_read(&t->regs[index]);
+	ret_val = io_read_data(ret_val, data_len);
+
 	return ret_val;
 }
 
-static void timer_write(struct io_device * self, uint32_t addr, uint32_t data, uint32_t data_len)
+static void timer_write(struct device *dev, uint32_t addr, uint32_t data, size_t count)
 {
+	struct timer *t = dev->priv;
+	struct io_register *regs;
 	uint32_t index = 0;
 	uint32_t temp = 0;
 	uint32_t only_read_mask = 0;
 	uint32_t valid_mask = 0;
-	
-	index = (addr - TIMER_BASE_ADDR) / 4;
-	
-	if (index >= 0 && index < TIMER_REG_CNT){
-		temp = hw.io_regs[index].value;
-		valid_mask = hw.io_regs[index].valid_mask;
-		only_read_mask = hw.io_regs[index].only_read_mask;
-		hw.io_regs[index].value = io_write_data_mask(temp, data, data_len, valid_mask, only_read_mask);
-		
-		
-		if (index == TIM_REG_PERIODL){
-			hw.set_period = hw.set_period &0xFFFF0000;
-			hw.set_period = hw.set_period | (data & 0xFFFF);
-			hw.curr_count = hw.set_period;
-			update_period_reg();
-		}
-		else if (index == TIM_REG_PERIODH){
-			hw.set_period = hw.set_period & 0xFFFF;
-			hw.set_period = hw.set_period | ((data & 0xFFFF) <<16);
-			hw.curr_count = hw.set_period;
-			update_period_reg();
-		}
-		else if (index == TIM_REG_STATUS){
-			if ((hw.io_regs[index].value & STATUS_TO_MASK) == 0){
-				clean_ipending(self->irq_enable_mask);
-			}
-		}
-	}
-}
 
-static int32_t timer_has_irq(struct io_device * self)
-{
-	int32_t ret_val = DEV_NO_IRQ;
-	uint32_t ctrl_reg_val = 0;
-	uint32_t status_reg_val = 0;
-	
-	ctrl_reg_val = hw.io_regs[TIM_REG_CTRL].value & hw.io_regs[TIM_REG_CTRL].valid_mask;
-	status_reg_val = hw.io_regs[TIM_REG_STATUS].value & hw.io_regs[TIM_REG_STATUS].valid_mask;
-	
-	if ((ctrl_reg_val & CTRL_ITO_MASK) == CTRL_ITO_MASK){
-		if ((status_reg_val & STATUS_TO_MASK) == STATUS_TO_MASK){
-			ret_val = DEV_HAS_IRQ;
-		}
+	index = (addr - dev->base) / 4;
+
+	if (index >= TIMER_REG_COUNT)
+		return;
+
+	temp = regs[index].value;
+	valid_mask = regs[index].valid_mask;
+	only_read_mask = regs[index].readonly_mask;
+	regs[index].value = io_write_data_mask(temp, data, data_len, valid_mask, only_read_mask);
+
+	if (index == TIMER_PERIODL_REG){
+		t->set_period &= 0xFFFF0000;
+		t->set_period |= data & 0xFFFF;
+		t->curr_count = t->set_period;
+		update_period_reg(t);
+	} else if (index == TIMER_PERIODH_REG) {
+		hw.set_period = hw.set_period & 0xFFFF;
+		hw.set_period = hw.set_period | ((data & 0xFFFF) <<16);
+		hw.curr_count = hw.set_period;
+		update_period_reg(t);
+	} else if (index == TIMER_STATUS_REG) {
+		if ((regs[index].value & STATUS_TO_MASK) == 0)
+			clean_ipending(dev->irq_mask);
 	}
-	return ret_val;
 }
+#endif
 
-static void copy_snapshot(void)
+static bool timer_has_irq(struct device *dev)
 {
-	hw.io_regs[TIM_REG_SNAPL].value = hw.io_regs[TIM_REG_PERIODL].value;
-	hw.io_regs[TIM_REG_SNAPH].value = hw.io_regs[TIM_REG_PERIODH].value;
-}
+	struct timer *t = dev->priv;
+	uint32_t ctrl_val = io_register_read(&t->regs[TIMER_CTRL_REG]);
+	uint32_t status_val = io_register_read(&t->regs[TIMER_STATUS_REG]);
 
-static void update_period_reg(void)
-{
-	hw.io_regs[TIM_REG_PERIODL].value = hw.curr_count & 0xFFFF;
-	hw.io_regs[TIM_REG_PERIODH].value = (hw.curr_count & 0xFFFF0000) >> 16;
-	//copy_snapshot();
+	if ((ctrl_val & TIMER_CTRL_ITO_MASK) == TIMER_CTRL_ITO_MASK)
+		if ((status_val & TIMER_STATUS_TO_MASK) == TIMER_STATUS_TO_MASK)
+			return true;
+
+	return false;
 }
 
-static void decrease_counter(void)
+static void decrease_counter(struct timer *t)
 {
-	if (hw.curr_count > 2){
-		hw.curr_count -= 2;
-	}
-	else {
-		hw.curr_count = 0;
-	}
-	update_period_reg();
+	if (t->curr_count > 2)
+		t->curr_count -= 2;
+	else
+		t->curr_count = 0;
+	update_period_reg(t);
 }
 
-static int32_t timer_can_decrease(void)
+static bool timer_can_decrease(struct timer *t)
 {
-	int32_t ret = SIM_TRUE;
-	uint32_t reg_ctrl_val = hw.io_regs[TIM_REG_CTRL].value;
-	
-	if ((reg_ctrl_val & CTRL_START_MASK) == 0){
-		ret = SIM_FALSE;
-		goto out;
-	}
-	
-	if ((reg_ctrl_val & CTRL_STOP_MASK) != 0){
-		ret = SIM_FALSE;
-		goto out;
-	}
-	
-	if (hw.set_period == hw.curr_count){
-		if ((reg_ctrl_val & CTRL_CONT_MASK) == 0){
-			ret = SIM_FALSE;
-			goto out;
-		}
-	}
-out:
-	return ret;
+	uint32_t ctrl_val = t->regs[TIMER_CTRL_REG].value;
+
+	/* Timer started? */
+	if ((ctrl_val & TIMER_CTRL_START_MASK) == 0)
+		return false;
+
+	/* Timer stopped? */
+	if ((ctrl_val & TIMER_CTRL_STOP_MASK) != 0)
+		return false;
+
+	/* If timer is not in continuous mode and counter has reached period */
+	if ((ctrl_val & TIMER_CTRL_CONT_MASK) == 0
+			&& t->set_period == t->curr_count)
+		return false;
+
+	return true;
 }
 
-static void update_status(void)
+static void update_status(struct timer *t)
 {
-	if(hw.curr_count <= 0){
-		hw.io_regs[TIM_REG_CTRL].value |= CTRL_ITO_MASK;
-		hw.curr_count = hw.set_period;
-		update_period_reg();
-		hw.io_regs[TIM_REG_STATUS].value |= STATUS_TO_MASK;
+	if (t->curr_count <= 0) {
+		t->regs[TIMER_CTRL_REG].value |= TIMER_CTRL_ITO_MASK;
+		t->curr_count = t->set_period;
+		update_period_reg(t);
+		t->regs[TIMER_STATUS_REG].value |= TIMER_STATUS_TO_MASK;
 	}
 }
 
-static void timer_simulate(struct io_device * self)
+static void timer_simulate(struct device *dev)
 {
-	if (timer_can_decrease() == SIM_TRUE) {
-		decrease_counter();
-		update_status();
+	struct timer *t = dev->priv;
+
+	if (timer_can_decrease(t)) {
+		decrease_counter(t);
+		update_status(t);
 	}
 }
 
-struct io_device timer_core = {
-	.name = "timer_core",
-	.init = timer_init,
-	.is_belong = timer_is_belong,
-	.read_data = timer_read,
-	.write_data = timer_write,
-	.has_irq = timer_has_irq,
-	.simulate = timer_simulate,
-	.irq_enable_mask = TIM_IRQ_MASK,
-};
-
+struct device timer_core = {
+	.name		= "Timer Core",
+	.base		= TIMER_BASE,
+	.size		= TIMER_SIZE,
+	.irq_mask	= IRQ_TO_MASK(TIMER_IRQ),
 
+	.init		= timer_init,
+	.is_dev_addr	= NULL,	/* use generic */
+	.has_irq	= timer_has_irq,
+	.simulate	= timer_simulate,
+};