1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
|
/*
* Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
* Copyright (C) 2010 chysun2000@gmail.com
*
* This file is part of nios2sim-ng.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef _NIOS2_H_
#define _NIOS2_H_
#include "instruction.h"
#define NIOS2_GP_REG_COUNT 32
/* there are really 32, but 16-31 are reserved for future use */
#define NIOS2_CTRL_REG_COUNT 16
struct nios2 {
/* General-Purpose Registers */
uint32_t gp_regs[NIOS2_GP_REG_COUNT];
/* Control Registers */
uint32_t ctrl_regs[NIOS2_CTRL_REG_COUNT];
/* Program counter */
uint32_t pc;
/* User or Supervisor mode */
int mode;
/* Configurable processor features */
bool has_mul; /* mul, muli */
bool has_mulx; /* mulxss, mulxsu, mulxuu */
bool has_div; /* div, divu */
bool has_mmu; /* Memory Management Unit */
};
/* Aliases for general-purpose registers */
enum {
zero = 0,
at,
et = 24,
bt,
gp,
sp,
fp,
ea,
ba,
ra,
};
/* Aliases for control registers */
enum {
status = 0,
estatus,
bstatus,
ienable,
ipending,
cpuid,
/* reserved */
exception = 7,
pteaddr,
tlbacc,
tlbmisc,
/* reserved */
badaddr = 12,
config,
mpubase,
mpuacc,
};
enum {
NIOS2_SUPERVISOR_MODE,
NIOS2_USER_MODE,
};
extern void nios2_cpu_reset(struct nios2 *cpu);
extern bool nios2_in_user_mode(struct nios2 *cpu);
extern bool nios2_in_supervisor_mode(struct nios2 *cpu);
extern uint32_t nios2_cpu_fetch_instr(struct nios2 *cpu, uint32_t *mem_base);
extern int nios2_cpu_execute_instr(struct nios2 *cpu, uint32_t instr);
#endif /* _NIOS2_H_ */
|
