Add ISP1362 component

2 files changed, 228 insertions, 0 deletions

diff --git a/lib/bus/avalon/ISP1362_CTRL.v b/lib/bus/avalon/ISP1362_CTRL.v
new file mode 100644
index 0000000..56f8020
--- /dev/null
+++ b/lib/bus/avalon/ISP1362_CTRL.v
@@ -0,0 +1,60 @@
+module ISP1362_CTRL (//Avalon Interface

+				clk, address, readdata, writedata, writedata_avalon_slave_1, chipselect_n, read_n, write_n, reset_n, write_n_avalon_slave_1, irq_n, irq_n_avalon_slave_1,

+				//Phillips USB controller

+				OTG_ADDR, OTG_DATA, OTG_CS_N, OTG_RD_N, OTG_WR_N, OTG_RST_N, OTG_INT0, OTG_INT1, OTG_FSPEED, OTG_LSPEED, OTG_DACK0_N, OTG_DACK1_N);

+	

+	//Avalon Interface

+	input clk, chipselect_n, read_n, write_n, reset_n, write_n_avalon_slave_1;

+	input [1:0] address;

+	input [15:0] writedata;

+	input [7:0] writedata_avalon_slave_1;

+	output [15:0] readdata;

+	output irq_n, irq_n_avalon_slave_1;

+	

+	//Phillips USB controller

+	output [1:0] OTG_ADDR;

+	inout [15:0] OTG_DATA;

+	output OTG_CS_N, OTG_RD_N, OTG_WR_N, OTG_RST_N;

+	input OTG_INT0, OTG_INT1;

+	output OTG_FSPEED, OTG_LSPEED, OTG_DACK0_N, OTG_DACK1_N;

+	

+	//Registers

+	reg [15:0] data, readdata;

+	reg [1:0] OTG_ADDR;

+	reg OTG_CS_N, OTG_RD_N, OTG_WR_N;

+	reg irq_n, irq_n_avalon_slave_1;

+	

+	//Assignments

+	assign OTG_RST_N = reset_n;

+	assign OTG_DATA = OTG_WR_N ? 16'hZZZZ : data;

+	assign OTG_DACK0_N = 1'b1, OTG_DACK1_N = 1'b1;

+	assign OTG_FSPEED = 0, OTG_LSPEED = 0;

+	

+	//Reset condition

+	always @ (posedge clk or negedge reset_n)

+	begin

+		if (reset_n==0)

+		begin

+			data 		<=  0;

+			readdata	<=	0;

+			OTG_ADDR	<=	0;

+			OTG_CS_N	<=	1;

+			OTG_RD_N	<=	1;

+			OTG_WR_N	<=	1;

+			irq_n					<=	1;

+			irq_n_avalon_slave_1	<=	1;

+		end

+		

+		else

+		begin

+			data		<=	writedata;

+			readdata	<=	OTG_DATA;

+			OTG_ADDR 	<=	address;

+			OTG_CS_N	<=	chipselect_n;

+			OTG_RD_N 	<=	read_n;

+			OTG_WR_N	<=	write_n;

+			irq_n					<=	OTG_INT0;

+			irq_n_avalon_slave_1	<=	OTG_INT1;

+		end

+	end

+endmodule

diff --git a/lib/bus/avalon/ISP1362_CTRL_hw.tcl b/lib/bus/avalon/ISP1362_CTRL_hw.tcl
new file mode 100644
index 0000000..dea80fd
--- /dev/null
+++ b/lib/bus/avalon/ISP1362_CTRL_hw.tcl
@@ -0,0 +1,168 @@
+# TCL File Generated by Component Editor 8.0
+# Thu Nov 20 17:00:55 CET 2008
+# DO NOT MODIFY
+
+
+# +-----------------------------------
+# | 
+# | ISP1362_CTRL "ISP1362_CTRL" v1.0
+# | null 2008.11.20.17:00:55
+# | 
+# | 
+# | /home/scratch/testSystem/ISP1362_CTRL.v
+# | 
+# |    ./ISP1362_CTRL.v syn, sim
+# | 
+# +-----------------------------------
+
+
+# +-----------------------------------
+# | module ISP1362_CTRL
+# | 
+set_module_property NAME ISP1362_CTRL
+set_module_property VERSION 1.0
+set_module_property GROUP ""
+set_module_property DISPLAY_NAME ISP1362_CTRL
+set_module_property TOP_LEVEL_HDL_FILE ISP1362_CTRL.v
+set_module_property TOP_LEVEL_HDL_MODULE ISP1362_CTRL
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE false
+set_module_property SIMULATION_MODEL_IN_VERILOG false
+set_module_property SIMULATION_MODEL_IN_VHDL false
+set_module_property SIMULATION_MODEL_HAS_TULIPS false
+set_module_property SIMULATION_MODEL_IS_OBFUSCATED false
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | files
+# | 
+add_file ISP1362_CTRL.v {SYNTHESIS SIMULATION}
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# | 
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point clock_reset
+# | 
+add_interface clock_reset clock end
+set_interface_property clock_reset ptfSchematicName ""
+
+add_interface_port clock_reset clk clk Input 1
+add_interface_port clock_reset reset_n reset_n Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point avalon_slave_0
+# | 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 holdTime 100
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
+set_interface_property avalon_slave_0 bridgesToMaster ""
+set_interface_property avalon_slave_0 isMemoryDevice false
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 addressSpan 4
+set_interface_property avalon_slave_0 timingUnits Nanoseconds
+set_interface_property avalon_slave_0 setupTime 100
+set_interface_property avalon_slave_0 writeWaitTime 100
+set_interface_property avalon_slave_0 writeWaitStates 100
+set_interface_property avalon_slave_0 isNonVolatileStorage false
+set_interface_property avalon_slave_0 addressAlignment NATIVE
+set_interface_property avalon_slave_0 readWaitStates 100
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 readWaitTime 100
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 printableDevice false
+
+set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 readdata readdata Output 16
+add_interface_port avalon_slave_0 writedata writedata Input 16
+add_interface_port avalon_slave_0 chipselect_n chipselect_n Input 1
+add_interface_port avalon_slave_0 read_n read_n Input 1
+add_interface_port avalon_slave_0 write_n write_n Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point avalon_slave_1
+# | 
+add_interface avalon_slave_1 avalon end
+set_interface_property avalon_slave_1 holdTime 100
+set_interface_property avalon_slave_1 linewrapBursts false
+set_interface_property avalon_slave_1 minimumUninterruptedRunLength 1
+set_interface_property avalon_slave_1 bridgesToMaster ""
+set_interface_property avalon_slave_1 isMemoryDevice false
+set_interface_property avalon_slave_1 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_1 timingUnits Nanoseconds
+set_interface_property avalon_slave_1 setupTime 100
+set_interface_property avalon_slave_1 writeWaitTime 100
+set_interface_property avalon_slave_1 writeWaitStates 100
+set_interface_property avalon_slave_1 isNonVolatileStorage false
+set_interface_property avalon_slave_1 addressAlignment NATIVE
+set_interface_property avalon_slave_1 readWaitStates 100
+set_interface_property avalon_slave_1 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_1 readWaitTime 100
+set_interface_property avalon_slave_1 readLatency 0
+set_interface_property avalon_slave_1 printableDevice false
+
+set_interface_property avalon_slave_1 ASSOCIATED_CLOCK clock_reset
+
+add_interface_port avalon_slave_1 write_n_avalon_slave_1 write_n Input 1
+add_interface_port avalon_slave_1 writedata_avalon_slave_1 writedata Input 8
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point conduit_end
+# | 
+add_interface conduit_end conduit end
+
+set_interface_property conduit_end ASSOCIATED_CLOCK clock_reset
+
+add_interface_port conduit_end OTG_ADDR export Output 2
+add_interface_port conduit_end OTG_DATA export Bidir 16
+add_interface_port conduit_end OTG_CS_N export Output 1
+add_interface_port conduit_end OTG_RD_N export Output 1
+add_interface_port conduit_end OTG_WR_N export Output 1
+add_interface_port conduit_end OTG_RST_N export Output 1
+add_interface_port conduit_end OTG_INT0 export Input 1
+add_interface_port conduit_end OTG_INT1 export Input 1
+add_interface_port conduit_end OTG_FSPEED export Output 1
+add_interface_port conduit_end OTG_LSPEED export Output 1
+add_interface_port conduit_end OTG_DACK0_N export Output 1
+add_interface_port conduit_end OTG_DACK1_N export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point interrupt_sender_1
+# | 
+add_interface interrupt_sender_1 interrupt end
+set_interface_property interrupt_sender_1 associatedAddressablePoint avalon_slave_1
+
+set_interface_property interrupt_sender_1 ASSOCIATED_CLOCK clock_reset
+
+add_interface_port interrupt_sender_1 irq_n_avalon_slave_1 irq_n Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point interrupt_sender_0
+# | 
+add_interface interrupt_sender_0 interrupt end
+set_interface_property interrupt_sender_0 associatedAddressablePoint avalon_slave_0
+
+set_interface_property interrupt_sender_0 ASSOCIATED_CLOCK clock_reset
+
+add_interface_port interrupt_sender_0 irq_n irq_n Output 1
+# | 
+# +-----------------------------------