diff options
author | Tobias Klauser <tklauser@distanz.ch> | 2010-08-02 11:00:08 +0200 |
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committer | Tobias Klauser <tklauser@distanz.ch> | 2010-08-02 11:00:08 +0200 |
commit | 643d40c1c4d154e0ac922402663349521c372e3a (patch) | |
tree | cd7ac85125dfdc3261fe279f428508b40bb71842 /lib/misc/components | |
parent | 0fffe741a1f1da87645e2833d06bc0851e6ff28e (diff) |
Add packages needed for TSE MAC
Diffstat (limited to 'lib/misc/components')
-rw-r--r-- | lib/misc/components/bibuf_async.vhd | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/lib/misc/components/bibuf_async.vhd b/lib/misc/components/bibuf_async.vhd new file mode 100644 index 0000000..915bae9 --- /dev/null +++ b/lib/misc/components/bibuf_async.vhd @@ -0,0 +1,69 @@ +------------------------------------------------------------------ +-- _____ ______ _____ - +-- |_ _| | ____|/ ____| Institute of Embedded Systems - +-- | | _ __ | |__ | (___ Zuercher Hochschule fuer - +-- | | | '_ \| __| \___ \ angewandte Wissenschaften - +-- _| |_| | | | |____ ____) | (University of Applied Sciences) - +-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +------------------------------------------------------------------ +-- +-- Project : InES library +-- Module : library ines_misc +-- Description : bidirectional port buffer without syncronisation +-- +-- $LastChangedDate: 2008-10-31 12:06:00 +0100 (Fri, 31 Oct 2008) $ +-- $Rev: 1905 $ +-- $Author: ffar $ +----------------------------------------------------------------- +-- +-- Change History +-- Date |Name |Modification +------------|----------|----------------------------------------- +-- 02.11.06 | ffar |file created +----------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +package bibuf_async_pkg is + component bibuf_async + port( + oe : in std_logic; + io : inout std_logic; + inp : in std_logic; + outp : out std_logic + ); + end component bibuf_async; +end package bibuf_async_pkg; + + + +library ieee; + use ieee.std_logic_1164.all; + + +entity bibuf_async is + port( + oe : in std_logic; + io : inout std_logic; + inp : in std_logic; + outp : out std_logic + ); + end bibuf_async; + +architecture rtl of bibuf_async is + +begin + + process(oe, io, inp) -- Behavioral representation + begin -- of tri-states. + if oe = '1' then + io <= inp; + outp <= inp; + else + io <= 'Z'; + outp <= io; + end if; + end process; + +end rtl;
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