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+------------------------------------------------------------------
+-- _____ ______ _____ -
+-- |_ _| | ____|/ ____| Institute of Embedded Systems -
+-- | | _ __ | |__ | (___ Zuercher Hochschule fuer -
+-- | | | '_ \| __| \___ \ angewandte Wissenschaften -
+-- _| |_| | | | |____ ____) | (University of Applied Sciences) -
+-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+------------------------------------------------------------------
+--
+-- Project : InES library
+-- Module : library ines_misc
+-- Description : bidirectional port buffer without syncronisation
+--
+-- $LastChangedDate: 2008-10-31 12:06:00 +0100 (Fri, 31 Oct 2008) $
+-- $Rev: 1905 $
+-- $Author: ffar $
+-----------------------------------------------------------------
+--
+-- Change History
+-- Date |Name |Modification
+------------|----------|-----------------------------------------
+-- 02.11.06 | ffar |file created
+-----------------------------------------------------------------
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+package bibuf_async_pkg is
+ component bibuf_async
+ port(
+ oe : in std_logic;
+ io : inout std_logic;
+ inp : in std_logic;
+ outp : out std_logic
+ );
+ end component bibuf_async;
+end package bibuf_async_pkg;
+
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+
+entity bibuf_async is
+ port(
+ oe : in std_logic;
+ io : inout std_logic;
+ inp : in std_logic;
+ outp : out std_logic
+ );
+ end bibuf_async;
+
+architecture rtl of bibuf_async is
+
+begin
+
+ process(oe, io, inp) -- Behavioral representation
+ begin -- of tri-states.
+ if oe = '1' then
+ io <= inp;
+ outp <= inp;
+ else
+ io <= 'Z';
+ outp <= io;
+ end if;
+ end process;
+
+end rtl; \ No newline at end of file