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authorTobias Klauser <tklauser@distanz.ch>2012-05-03 08:40:31 +0200
committerTobias Klauser <tklauser@distanz.ch>2012-05-03 08:40:31 +0200
commit98feedbabc40f4faea1654419ddf6748ee850955 (patch)
tree1808a2863e0abcb9a3749c447f7738ebe80f2c8e /lib
parenta61a0a0cb72ad6b1fe1816a886fe5aa23c8b1442 (diff)
Add more InES clock sync stuff
Diffstat (limited to 'lib')
-rw-r--r--lib/misc/components/buf_sync.vhd84
-rw-r--r--lib/misc/components/input_sync.vhd75
2 files changed, 159 insertions, 0 deletions
diff --git a/lib/misc/components/buf_sync.vhd b/lib/misc/components/buf_sync.vhd
new file mode 100644
index 0000000..bcc48ad
--- /dev/null
+++ b/lib/misc/components/buf_sync.vhd
@@ -0,0 +1,84 @@
+------------------------------------------------------------------
+-- _____ ______ _____ -
+-- |_ _| | ____|/ ____| Institute of Embedded Systems -
+-- | | _ __ | |__ | (___ Zuercher Hochschule fuer -
+-- | | | '_ \| __| \___ \ angewandte Wissenschaften -
+-- _| |_| | | | |____ ____) | (University of Applied Sciences) -
+-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+------------------------------------------------------------------
+--
+-- Project : InES library
+-- Module : library ines_misc
+-- Description : port buffer with clock domain syncronisation
+--
+-- $LastChangedDate$
+-- $Rev $
+-- $Author $
+-----------------------------------------------------------------
+--
+-- Change History
+-- Date |Name |Modification
+------------|----------|-----------------------------------------
+-- 20.06.08 | ffar |file created
+-----------------------------------------------------------------
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+package buf_sync_pkg is
+ component buf_sync
+ generic(
+ G_NUM_BUF : natural := 1
+ );
+ port(
+ clk_i : in std_logic;
+ reset_n_i : in std_logic;
+ inp_i : in std_logic_vector(G_NUM_BUF-1 downto 0);
+ outp_o : out std_logic_vector(G_NUM_BUF-1 downto 0)
+ );
+ end component buf_sync;
+end package buf_sync_pkg;
+
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+
+entity buf_sync is
+ generic(
+ G_NUM_BUF : natural := 1
+ );
+ port(
+ clk_i : in std_logic;
+ reset_n_i : in std_logic;
+ inp_i : in std_logic_vector(G_NUM_BUF-1 downto 0);
+ outp_o : out std_logic_vector(G_NUM_BUF-1 downto 0)
+ );
+end buf_sync;
+
+architecture rtl of buf_sync is
+
+ signal inp_f : std_logic_vector(inp_i'range);
+ signal inp_ff : std_logic_vector(inp_i'range);
+
+begin
+
+ outp_o <= inp_ff;
+
+ ff_gen : for i in inp_i'range generate
+ begin
+ ff_prc : process(clk_i, reset_n_i)
+ begin
+ if reset_n_i = '0' then
+ inp_f(i) <= '0';
+ inp_ff(i) <= '0';
+ elsif clk_i'event and clk_i = '1' then -- Creates the flipflops
+ inp_f(i) <= inp_i(i);
+ inp_ff(i) <= inp_f(i);
+ end if;
+ end process ff_prc;
+ end generate ff_gen;
+
+end rtl; \ No newline at end of file
diff --git a/lib/misc/components/input_sync.vhd b/lib/misc/components/input_sync.vhd
new file mode 100644
index 0000000..4e3ac57
--- /dev/null
+++ b/lib/misc/components/input_sync.vhd
@@ -0,0 +1,75 @@
+------------------------------------------------------------------
+-- _____ ______ _____ -
+-- |_ _| | ____|/ ____| Institute of Embedded Systems -
+-- | | _ __ | |__ | (___ Zuercher Hochschule fuer -
+-- | | | '_ \| __| \___ \ angewandte Wissenschaften -
+-- _| |_| | | | |____ ____) | (University of Applied Sciences) -
+-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+------------------------------------------------------------------
+--
+-- Project : SInet
+-- Module : synthesis library ines_misc
+-- Description : input synchronisytion
+--
+-- $LastChangedDate $
+-- $Rev$
+-- $Author$
+-----------------------------------------------------------------
+--
+-- Change History
+-- Date |Name |Modification
+-----------------------------------------------------------------
+-- 01.02.08 | ffar + beut | file created based on library component
+-----------------------------------------------------------------
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+package input_sync_pkg is
+ component input_sync
+ generic(
+ G_INIT_VALUE : std_logic := '0'
+ );
+ port(
+ clk_i : in std_logic;
+ reset_n_i : in std_logic;
+ async_signal_i : in std_logic;
+ sync_signal_o : out std_logic
+ );
+ end component input_sync;
+end package input_sync_pkg;
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+entity input_sync is
+ generic(
+ G_INIT_VALUE : std_logic := '0'
+ );
+ port(
+ clk_i : in std_logic;
+ reset_n_i : in std_logic;
+ async_signal_i : in std_logic;
+ sync_signal_o : out std_logic
+ );
+ end input_sync;
+
+architecture rtl of input_sync is
+
+ signal sync_signal_f : std_logic;
+
+begin
+ sync_prc : process(clk_i, reset_n_i, async_signal_i, sync_signal_f)
+ begin
+ if reset_n_i = '0' then
+ sync_signal_f <= G_INIT_VALUE;
+ sync_signal_o <= G_INIT_VALUE;
+ elsif clk_i'event and clk_i = '1' then
+ sync_signal_f <= async_signal_i;
+ sync_signal_o <= sync_signal_f;
+ end if;
+ end process sync_prc;
+end rtl; \ No newline at end of file