diff options
Diffstat (limited to 'lib/misc')
| -rw-r--r-- | lib/misc/components/bibuf_async.vhd | 69 | ||||
| -rw-r--r-- | lib/misc/ines_vhdl_lib_base_pkg.vhd | 129 | ||||
| -rw-r--r-- | lib/misc/reduce_pkg.vhd | 424 |
3 files changed, 622 insertions, 0 deletions
diff --git a/lib/misc/components/bibuf_async.vhd b/lib/misc/components/bibuf_async.vhd new file mode 100644 index 0000000..915bae9 --- /dev/null +++ b/lib/misc/components/bibuf_async.vhd @@ -0,0 +1,69 @@ +------------------------------------------------------------------ +-- _____ ______ _____ - +-- |_ _| | ____|/ ____| Institute of Embedded Systems - +-- | | _ __ | |__ | (___ Zuercher Hochschule fuer - +-- | | | '_ \| __| \___ \ angewandte Wissenschaften - +-- _| |_| | | | |____ ____) | (University of Applied Sciences) - +-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +------------------------------------------------------------------ +-- +-- Project : InES library +-- Module : library ines_misc +-- Description : bidirectional port buffer without syncronisation +-- +-- $LastChangedDate: 2008-10-31 12:06:00 +0100 (Fri, 31 Oct 2008) $ +-- $Rev: 1905 $ +-- $Author: ffar $ +----------------------------------------------------------------- +-- +-- Change History +-- Date |Name |Modification +------------|----------|----------------------------------------- +-- 02.11.06 | ffar |file created +----------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +package bibuf_async_pkg is + component bibuf_async + port( + oe : in std_logic; + io : inout std_logic; + inp : in std_logic; + outp : out std_logic + ); + end component bibuf_async; +end package bibuf_async_pkg; + + + +library ieee; + use ieee.std_logic_1164.all; + + +entity bibuf_async is + port( + oe : in std_logic; + io : inout std_logic; + inp : in std_logic; + outp : out std_logic + ); + end bibuf_async; + +architecture rtl of bibuf_async is + +begin + + process(oe, io, inp) -- Behavioral representation + begin -- of tri-states. + if oe = '1' then + io <= inp; + outp <= inp; + else + io <= 'Z'; + outp <= io; + end if; + end process; + +end rtl;
\ No newline at end of file diff --git a/lib/misc/ines_vhdl_lib_base_pkg.vhd b/lib/misc/ines_vhdl_lib_base_pkg.vhd new file mode 100644 index 0000000..e9cd602 --- /dev/null +++ b/lib/misc/ines_vhdl_lib_base_pkg.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------ +-- _____ ______ _____ - +-- |_ _| | ____|/ ____| Institute of Embedded Systems - +-- | | _ __ | |__ | (___ Zuercher Hochschule fuer - +-- | | | '_ \| __| \___ \ angewandte Wissenschaften - +-- _| |_| | | | |____ ____) | (University of Applied Sciences) - +-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +------------------------------------------------------------------ +-- +-- Project : SInet +-- Module : library ines_misc +-- Description : Base package of ines misc library +-- +-- $LastChangedDate: 2007-11-02 14:43:24 +0100 (Fri, 02 Nov 2007) $ +-- $Rev: 403 $ +-- $Author: ffar $ +----------------------------------------------------------------- +-- +-- Change History +-- Date |Name |Modification +------------|----------|----------------------------------------- +-- 02.11.07 | ffar |file created +----------------------------------------------------------------- + + +library ieee; + use ieee.std_logic_1164.all; + + + +package ines_vhdl_lib_base_pkg is + + -- constants + + -- types + subtype std_logic_vector_1 is std_logic_vector(0 downto 0); + type std_logic_array_1 is array(natural range <>) of std_logic_vector_1; + subtype std_logic_vector_2 is std_logic_vector(1 downto 0); + type std_logic_array_2 is array(natural range <>) of std_logic_vector_2; + subtype std_logic_vector_3 is std_logic_vector(2 downto 0); + type std_logic_array_3 is array(natural range <>) of std_logic_vector_3; + subtype std_logic_vector_4 is std_logic_vector(3 downto 0); + type std_logic_array_4 is array(natural range <>) of std_logic_vector_4; + subtype std_logic_vector_5 is std_logic_vector(4 downto 0); + type std_logic_array_5 is array(natural range <>) of std_logic_vector_5; + subtype std_logic_vector_6 is std_logic_vector(5 downto 0); + type std_logic_array_6 is array(natural range <>) of std_logic_vector_6; + subtype std_logic_vector_7 is std_logic_vector(6 downto 0); + type std_logic_array_7 is array(natural range <>) of std_logic_vector_7; + subtype std_logic_vector_8 is std_logic_vector(7 downto 0); + type std_logic_array_8 is array(natural range <>) of std_logic_vector_8; + subtype std_logic_vector_9 is std_logic_vector(8 downto 0); + type std_logic_array_9 is array(natural range <>) of std_logic_vector_9; + subtype std_logic_vector_10 is std_logic_vector(9 downto 0); + type std_logic_array_10 is array(natural range <>) of std_logic_vector_10; + subtype std_logic_vector_11 is std_logic_vector(10 downto 0); + type std_logic_array_11 is array(natural range <>) of std_logic_vector_11; + subtype std_logic_vector_12 is std_logic_vector(11 downto 0); + type std_logic_array_12 is array(natural range <>) of std_logic_vector_12; + subtype std_logic_vector_13 is std_logic_vector(12 downto 0); + type std_logic_array_13 is array(natural range <>) of std_logic_vector_13; + subtype std_logic_vector_14 is std_logic_vector(13 downto 0); + type std_logic_array_14 is array(natural range <>) of std_logic_vector_14; + subtype std_logic_vector_15 is std_logic_vector(14 downto 0); + type std_logic_array_15 is array(natural range <>) of std_logic_vector_15; + subtype std_logic_vector_16 is std_logic_vector(15 downto 0); + type std_logic_array_16 is array(natural range <>) of std_logic_vector_16; + subtype std_logic_vector_17 is std_logic_vector(16 downto 0); + type std_logic_array_17 is array(natural range <>) of std_logic_vector_17; + subtype std_logic_vector_18 is std_logic_vector(17 downto 0); + type std_logic_array_18 is array(natural range <>) of std_logic_vector_18; + subtype std_logic_vector_19 is std_logic_vector(18 downto 0); + type std_logic_array_19 is array(natural range <>) of std_logic_vector_19; + subtype std_logic_vector_20 is std_logic_vector(19 downto 0); + type std_logic_array_20 is array(natural range <>) of std_logic_vector_20; + subtype std_logic_vector_21 is std_logic_vector(20 downto 0); + type std_logic_array_21 is array(natural range <>) of std_logic_vector_21; + subtype std_logic_vector_22 is std_logic_vector(21 downto 0); + type std_logic_array_22 is array(natural range <>) of std_logic_vector_22; + subtype std_logic_vector_23 is std_logic_vector(22 downto 0); + type std_logic_array_23 is array(natural range <>) of std_logic_vector_23; + subtype std_logic_vector_24 is std_logic_vector(23 downto 0); + type std_logic_array_24 is array(natural range <>) of std_logic_vector_24; + subtype std_logic_vector_25 is std_logic_vector(24 downto 0); + type std_logic_array_25 is array(natural range <>) of std_logic_vector_25; + subtype std_logic_vector_26 is std_logic_vector(25 downto 0); + type std_logic_array_26 is array(natural range <>) of std_logic_vector_26; + subtype std_logic_vector_27 is std_logic_vector(26 downto 0); + type std_logic_array_27 is array(natural range <>) of std_logic_vector_27; + subtype std_logic_vector_28 is std_logic_vector(27 downto 0); + type std_logic_array_28 is array(natural range <>) of std_logic_vector_28; + subtype std_logic_vector_29 is std_logic_vector(28 downto 0); + type std_logic_array_29 is array(natural range <>) of std_logic_vector_29; + subtype std_logic_vector_30 is std_logic_vector(29 downto 0); + type std_logic_array_30 is array(natural range <>) of std_logic_vector_30; + subtype std_logic_vector_31 is std_logic_vector(30 downto 0); + type std_logic_array_31 is array(natural range <>) of std_logic_vector_31; + subtype std_logic_vector_32 is std_logic_vector(31 downto 0); + type std_logic_array_32 is array(natural range <>) of std_logic_vector_32; + subtype std_logic_vector_34 is std_logic_vector(33 downto 0); + type std_logic_array_34 is array(natural range <>) of std_logic_vector_34; + subtype std_logic_vector_36 is std_logic_vector(35 downto 0); + type std_logic_array_36 is array(natural range <>) of std_logic_vector_36; + subtype std_logic_vector_64 is std_logic_vector(63 downto 0); + type std_logic_array_64 is array(natural range <>) of std_logic_vector_64; + subtype std_logic_vector_72 is std_logic_vector(71 downto 0); + type std_logic_array_72 is array(natural range <>) of std_logic_vector_72; + + -- functions + function zeros (n:natural) return std_logic_vector; + + +end package ines_vhdl_lib_base_pkg; + + + +package body ines_vhdl_lib_base_pkg is + + function zeros (n:natural) return std_logic_vector is + variable result: std_logic_vector(n-1 downto 0); + begin + for i in 0 to n-1 loop + result(i) := '0'; + end loop; + return result; + end; + +end package body ines_vhdl_lib_base_pkg; + diff --git a/lib/misc/reduce_pkg.vhd b/lib/misc/reduce_pkg.vhd new file mode 100644 index 0000000..8a4d80b --- /dev/null +++ b/lib/misc/reduce_pkg.vhd @@ -0,0 +1,424 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright 2002 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE [Draft] Standard 1076.3 +-- reduce_pkg +-- This source file may not be copied, sold, or included +-- with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this +-- [draft] standard and may be distributed in compiled form in any manner so +-- long as the compiled form does not allow direct decompilation of the +-- original source file. This source file may be copied for individaul use +-- between licensed users. +-- +-- The IEEE disclaims any responsibility or liability for damages resulting +-- from misinterpretation or misue of said information by the user. +-- +-- [This source file represents a portion of the IEEE Draft Standard and is +-- unapproved and subject to change.] +-- +-- < statement about permission to modify > +-- +-- Title : REDUCE_PKG < IEEE std # 1076.3 > +-- +-- Library : This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL/Synthesis, PAR 1076.3 +-- +-- Purpose : Reduction operations. This allows a vector to +-- be collapsed into a signle bit. Similar to the built +-- in functions in Verilog. +-- +-- Limitation: +-- +-- -------------------------------------------------------------------- +-- modification history : +-- -------------------------------------------------------------------- +-- Version: 1.3 +-- Date : 8 July 2002 +-- Added "to_x01" on all inputs. +-- Made "and_reduce" return a "1" in the NULL case. +-- ------------------------------------------------------------------------- +-- Version: 1.2 +-- Date : 21 June 2002 +-- Fixed some basic logic errors. +-- ------------------------------------------------------------------------- +-- Version: 1.1 +-- Date : 13 May 2002 +-- Modified to deal with null arrays, added IEEE header. +-- ------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +-- Package definition +package reduce_pack is + FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of and'ing all of the bits of the vector. + + FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of nand'ing all of the bits of the vector. + + FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of or'ing all of the bits of the vector. + + FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of nor'ing all of the bits of the vector. + + FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of xor'ing all of the bits of the vector. + + FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of xnor'ing all of the bits of the vector. + + FUNCTION and_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of and'ing all of the bits of the vector. + + FUNCTION nand_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of nand'ing all of the bits of the vector. + + FUNCTION or_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of or'ing all of the bits of the vector. + + FUNCTION nor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of nor'ing all of the bits of the vector. + + FUNCTION xor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of xor'ing all of the bits of the vector. + + FUNCTION xnor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of xnor'ing all of the bits of the vector. + + FUNCTION and_reduce(arg : SIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of and'ing all of the bits of the vector. + + FUNCTION nand_reduce(arg : SIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of nand'ing all of the bits of the vector. + + FUNCTION or_reduce(arg : SIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of or'ing all of the bits of the vector. + + FUNCTION nor_reduce(arg : SIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of nor'ing all of the bits of the vector. + + FUNCTION xor_reduce(arg : SIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of xor'ing all of the bits of the vector. + + FUNCTION xnor_reduce(arg : SIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of xnor'ing all of the bits of the vector. + + FUNCTION and_reduce(arg : UNSIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of and'ing all of the bits of the vector. + + FUNCTION nand_reduce(arg : UNSIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of nand'ing all of the bits of the vector. + + FUNCTION or_reduce(arg : UNSIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of or'ing all of the bits of the vector. + + FUNCTION nor_reduce(arg : UNSIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of nor'ing all of the bits of the vector. + + FUNCTION xor_reduce(arg : UNSIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of xor'ing all of the bits of the vector. + + FUNCTION xnor_reduce(arg : UNSIGNED) RETURN STD_LOGIC; + -- Result subtype: STD_LOGIC. + -- Result: Result of xnor'ing all of the bits of the vector. + + -- bit_vector versions + FUNCTION and_reduce(arg : BIT_VECTOR) RETURN BIT; + -- Result subtype: BIT. + -- Result: Result of and'ing all of the bits of the vector. + + FUNCTION nand_reduce(arg : BIT_VECTOR) RETURN BIT; + -- Result subtype: BIT. + -- Result: Result of nand'ing all of the bits of the vector. + + FUNCTION or_reduce(arg : BIT_VECTOR) RETURN BIT; + -- Result subtype: BIT. + -- Result: Result of or'ing all of the bits of the vector. + + FUNCTION nor_reduce(arg : BIT_VECTOR) RETURN BIT; + -- Result subtype: BIT. + -- Result: Result of nor'ing all of the bits of the vector. + + FUNCTION xor_reduce(arg : BIT_VECTOR) RETURN BIT; + -- Result subtype: BIT. + -- Result: Result of xor'ing all of the bits of the vector. + + FUNCTION xnor_reduce(arg : BIT_VECTOR) RETURN BIT; + -- Result subtype: BIT. + -- Result: Result of xnor'ing all of the bits of the vector. + +end reduce_Pack; + +-- Package body. +package body reduce_Pack is + +-- done in a recursively called function. + function and_reduce (arg : std_logic_vector ) + return std_logic is + variable Upper, Lower : std_logic; + variable Half : integer; + variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 ); + variable Result : std_logic; + begin + if (arg'LENGTH < 1) then -- In the case of a NULL range + Result := '1'; -- Change for version 1.3 + else + BUS_int := to_ux01 (arg); + if ( BUS_int'length = 1 ) then + Result := BUS_int ( BUS_int'left ); + elsif ( BUS_int'length = 2 ) then + Result := BUS_int ( BUS_int'right ) and BUS_int ( BUS_int'left ); + else + Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right; + Upper := and_reduce ( BUS_int ( BUS_int'left downto Half )); + Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right )); + Result := Upper and Lower; + end if; + end if; + return Result; + end; + + function nand_reduce (arg : std_logic_vector ) + return std_logic is + begin + return not and_reduce (arg); + end; + + function or_reduce (arg : std_logic_vector ) + return std_logic is + variable Upper, Lower : std_logic; + variable Half : integer; + variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 ); + variable Result : std_logic; + begin + if (arg'LENGTH < 1) then -- In the case of a NULL range + Result := '0'; + else + BUS_int := to_ux01 (arg); + if ( BUS_int'length = 1 ) then + Result := BUS_int ( BUS_int'left ); + elsif ( BUS_int'length = 2 ) then + Result := BUS_int ( BUS_int'right ) or BUS_int ( BUS_int'left ); + else + Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right; + Upper := or_reduce ( BUS_int ( BUS_int'left downto Half )); + Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right )); + Result := Upper or Lower; + end if; + end if; + return Result; + end; + + function nor_reduce (arg : std_logic_vector ) + return std_logic is + begin + return not or_reduce ( arg ); + end; + + function xor_reduce (arg : std_logic_vector ) + return std_logic is + variable Upper, Lower : std_logic; + variable Half : integer; + variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 ); + variable Result : std_logic; + begin + if (arg'LENGTH < 1) then -- In the case of a NULL range + Result := '0'; + else + BUS_int := to_ux01 (arg); + if ( BUS_int'length = 1 ) then + Result := BUS_int ( BUS_int'left ); + elsif ( BUS_int'length = 2 ) then + Result := BUS_int ( BUS_int'right ) xor BUS_int ( BUS_int'left ); + else + Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right; + Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half )); + Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right )); + Result := Upper xor Lower; + end if; + end if; + return Result; + end; + + function xnor_reduce (arg : std_logic_vector ) + return std_logic is + begin + return not xor_reduce ( arg ); + end; + + function and_reduce (arg : std_ulogic_vector ) + return std_logic is + begin + return and_reduce (std_logic_vector ( arg )); + end; + + function and_reduce (arg : SIGNED ) + return std_logic is + begin + return and_reduce (std_logic_vector ( arg )); + end; + + function and_reduce (arg : UNSIGNED ) + return std_logic is + begin + return and_reduce (std_logic_vector ( arg )); + end; + + function nand_reduce (arg : std_ulogic_vector ) + return std_logic is + begin + return nand_reduce (std_logic_vector ( arg )); + end; + + function nand_reduce (arg : SIGNED ) + return std_logic is + begin + return nand_reduce (std_logic_vector ( arg )); + end; + + function nand_reduce (arg : UNSIGNED ) + return std_logic is + begin + return nand_reduce (std_logic_vector ( arg )); + end; + + function or_reduce (arg : std_ulogic_vector ) + return std_logic is + begin + return or_reduce (std_logic_vector ( arg )); + end; + + function or_reduce (arg : SIGNED ) + return std_logic is + begin + return or_reduce (std_logic_vector ( arg )); + end; + + function or_reduce (arg : UNSIGNED ) + return std_logic is + begin + return or_reduce (std_logic_vector ( arg )); + end; + + function nor_reduce (arg : std_ulogic_vector ) + return std_logic is + begin + return nor_reduce (std_logic_vector ( arg )); + end; + + function nor_reduce (arg : SIGNED ) + return std_logic is + begin + return nor_reduce (std_logic_vector ( arg )); + end; + + function nor_reduce (arg : UNSIGNED ) + return std_logic is + begin + return nor_reduce (std_logic_vector ( arg )); + end; + + function xor_reduce (arg : std_ulogic_vector ) + return std_logic is + begin + return xor_reduce (std_logic_vector ( arg )); + end; + + function xor_reduce (arg : SIGNED ) + return std_logic is + begin + return xor_reduce (std_logic_vector ( arg )); + end; + + function xor_reduce (arg : UNSIGNED ) + return std_logic is + begin + return xor_reduce (std_logic_vector ( arg )); + end; + + function xnor_reduce (arg : std_ulogic_vector ) + return std_logic is + begin + return xnor_reduce (std_logic_vector ( arg )); + end; + + function xnor_reduce (arg : SIGNED ) + return std_logic is + begin + return xnor_reduce (std_logic_vector ( arg )); + end; + + function xnor_reduce (arg : UNSIGNED ) + return std_logic is + begin + return xnor_reduce (std_logic_vector ( arg )); + end; + + function and_reduce (arg : bit_vector ) + return bit is + begin + return to_bit (and_reduce (to_stdlogicvector ( arg ))); + end; + + function nand_reduce (arg : bit_vector ) + return bit is + begin + return to_bit (nand_reduce (to_stdlogicvector ( arg ))); + end; + + function or_reduce (arg : bit_vector ) + return bit is + begin + return to_bit (or_reduce (to_stdlogicvector ( arg ))); + end; + + function nor_reduce (arg : bit_vector ) + return bit is + begin + return to_bit (nor_reduce (to_stdlogicvector ( arg ))); + end; + + function xor_reduce (arg : bit_vector ) + return bit is + begin + return to_bit (xor_reduce (to_stdlogicvector ( arg ))); + end; + + function xnor_reduce (arg : bit_vector ) + return bit is + begin + return to_bit (xnor_reduce (to_stdlogicvector ( arg ))); + end; + +end reduce_pack; + + |