diff options
Diffstat (limited to 'quartus/dionysos_nios2mmu.sopc')
| -rw-r--r-- | quartus/dionysos_nios2mmu.sopc | 324 |
1 files changed, 310 insertions, 14 deletions
diff --git a/quartus/dionysos_nios2mmu.sopc b/quartus/dionysos_nios2mmu.sopc index 9d5005e..e99297b 100644 --- a/quartus/dionysos_nios2mmu.sopc +++ b/quartus/dionysos_nios2mmu.sopc @@ -9,6 +9,11 @@ value = "16"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element jtag_uart_0.avalon_jtag_slave { @@ -61,6 +66,11 @@ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element clk_0 { @@ -109,6 +119,30 @@ type = "String"; } } + element cpu_0_converter + { + datum _sortIndex + { + value = "18"; + type = "int"; + } + } + element cpu_0_ffs_inst + { + datum _sortIndex + { + value = "19"; + type = "int"; + } + } + element cpu_0_fls_inst + { + datum _sortIndex + { + value = "20"; + type = "int"; + } + } element sgdma_tx.csr { datum _lockedAddress @@ -147,6 +181,11 @@ value = "{}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element dionysos_nios2mmu { @@ -176,6 +215,11 @@ value = "{}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element cpu_0.jtag_debug_module { @@ -202,12 +246,17 @@ value = "{}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element onchip_memory2_0 { datum _sortIndex { - value = "3"; + value = "2"; type = "int"; } datum megawizard_uipreferences @@ -215,8 +264,52 @@ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } - element onchip_memory2_0.s1 + element pio_dipswitch + { + datum _sortIndex + { + value = "22"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element pio_leds_board + { + datum _sortIndex + { + value = "21"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element pio_leds_front + { + datum _sortIndex + { + value = "17"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; + type = "String"; + } + } + element pio_leds_front.s1 { datum _lockedAddress { @@ -225,7 +318,20 @@ } datum baseAddress { - value = "75505664"; + value = "71303200"; + type = "long"; + } + } + element descriptor_memory.s1 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "75759616"; type = "long"; } } @@ -242,7 +348,7 @@ type = "long"; } } - element timer_0.s1 + element pio_dipswitch.s1 { datum _lockedAddress { @@ -251,7 +357,20 @@ } datum baseAddress { - value = "71303168"; + value = "71303264"; + type = "long"; + } + } + element pio_leds_board.s1 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "71303232"; type = "long"; } } @@ -281,7 +400,7 @@ type = "long"; } } - element descriptor_memory.s1 + element cfi_flash_0.s1 { datum _lockedAddress { @@ -290,11 +409,11 @@ } datum baseAddress { - value = "75759616"; + value = "67108864"; type = "long"; } } - element cfi_flash_0.s1 + element onchip_memory2_0.s1 { datum _lockedAddress { @@ -303,7 +422,20 @@ } datum baseAddress { - value = "67108864"; + value = "75505664"; + type = "long"; + } + } + element timer_0.s1 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "71303168"; type = "long"; } } @@ -324,7 +456,7 @@ { datum _sortIndex { - value = "4"; + value = "3"; type = "int"; } datum megawizard_uipreferences @@ -332,6 +464,11 @@ value = "{}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element sgdma_rx { @@ -345,6 +482,11 @@ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element sgdma_tx { @@ -358,12 +500,17 @@ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element sysid { datum _sortIndex { - value = "2"; + value = "4"; type = "int"; } datum megawizard_uipreferences @@ -371,6 +518,11 @@ value = "{}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element timer_0 { @@ -384,6 +536,11 @@ value = "{}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element tri_state_bridge_0 { @@ -397,6 +554,11 @@ value = "{}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element tse_mac { @@ -410,6 +572,11 @@ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element uart_0 { @@ -423,6 +590,11 @@ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element watchdog_timer { @@ -436,6 +608,11 @@ value = "{}"; type = "String"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } } ]]></parameter> @@ -444,8 +621,8 @@ <parameter name="hardcopyCompatible" value="false" /> <parameter name="hdlLanguage" value="VHDL" /> <parameter name="projectName">dionysos_nios2mmu.qpf</parameter> - <parameter name="systemHash" value="-88262254885" /> - <parameter name="timeStamp" value="1308843850996" /> + <parameter name="systemHash" value="-101819761844" /> + <parameter name="timeStamp" value="1331195628538" /> <module name="clk_0" kind="clock_source" version="9.1" enabled="1"> <parameter name="clockFrequency" value="50000000" /> <parameter name="clockFrequencyKnown" value="true" /> @@ -457,7 +634,7 @@ <parameter name="setting_shadowRegisterSets" value="0" /> <parameter name="setting_preciseSlaveAccessErrorException" value="false" /> <parameter name="setting_preciseIllegalMemAccessException" value="false" /> - <parameter name="setting_preciseDivisionErrorException" value="false" /> + <parameter name="setting_preciseDivisionErrorException" value="true" /> <parameter name="setting_performanceCounter" value="false" /> <parameter name="setting_perfCounterWidth" value="_32" /> <parameter name="setting_interruptControllerType" value="Internal" /> @@ -781,6 +958,64 @@ </module> <module name="sysid" kind="altera_avalon_sysid" version="9.1" enabled="1" /> <module name="ISP1362" kind="ISP1362_CTRL" version="1.0" enabled="1" /> + <module + name="pio_leds_front" + kind="altera_avalon_pio" + version="9.1" + enabled="1"> + <parameter name="bitClearingEdgeCapReg" value="false" /> + <parameter name="bitModifyingOutReg" value="true" /> + <parameter name="captureEdge" value="false" /> + <parameter name="direction" value="Output" /> + <parameter name="edgeType" value="RISING" /> + <parameter name="generateIRQ" value="false" /> + <parameter name="irqType" value="LEVEL" /> + <parameter name="resetValue" value="0" /> + <parameter name="simDoTestBenchWiring" value="false" /> + <parameter name="simDrivenValue" value="0" /> + <parameter name="width" value="16" /> + </module> + <module + name="cpu_0_converter" + kind="altera_nios_custom_instr_endian_converter" + version="6.1" + enabled="1" /> + <module name="cpu_0_ffs_inst" kind="ffs" version="1.0" enabled="1" /> + <module name="cpu_0_fls_inst" kind="fls" version="1.0" enabled="1" /> + <module + name="pio_leds_board" + kind="altera_avalon_pio" + version="9.1" + enabled="1"> + <parameter name="bitClearingEdgeCapReg" value="false" /> + <parameter name="bitModifyingOutReg" value="true" /> + <parameter name="captureEdge" value="false" /> + <parameter name="direction" value="Output" /> + <parameter name="edgeType" value="RISING" /> + <parameter name="generateIRQ" value="false" /> + <parameter name="irqType" value="LEVEL" /> + <parameter name="resetValue" value="0" /> + <parameter name="simDoTestBenchWiring" value="false" /> + <parameter name="simDrivenValue" value="0" /> + <parameter name="width" value="4" /> + </module> + <module + name="pio_dipswitch" + kind="altera_avalon_pio" + version="9.1" + enabled="1"> + <parameter name="bitClearingEdgeCapReg" value="true" /> + <parameter name="bitModifyingOutReg" value="false" /> + <parameter name="captureEdge" value="true" /> + <parameter name="direction" value="Input" /> + <parameter name="edgeType" value="RISING" /> + <parameter name="generateIRQ" value="true" /> + <parameter name="irqType" value="EDGE" /> + <parameter name="resetValue" value="0" /> + <parameter name="simDoTestBenchWiring" value="false" /> + <parameter name="simDrivenValue" value="0" /> + <parameter name="width" value="4" /> + </module> <connection kind="clock" version="9.1" start="clk_0.clk" end="cpu_0.clk" /> <connection kind="avalon" @@ -1113,4 +1348,65 @@ end="ISP1362.interrupt_sender_0"> <parameter name="irqNumber" value="7" /> </connection> + <connection kind="clock" version="9.1" start="clk_0.clk" end="pio_leds_front.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="pio_leds_front.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x04400020" /> + </connection> + <connection + kind="nios_custom_instruction" + version="9.1" + start="cpu_0.custom_instruction_master" + end="cpu_0_converter.s1"> + <parameter name="CIName" value="converter" /> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0" /> + </connection> + <connection + kind="nios_custom_instruction" + version="9.1" + start="cpu_0.custom_instruction_master" + end="cpu_0_ffs_inst.nios_custom_instruction_slave_0"> + <parameter name="CIName" value="ffs_inst" /> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="1" /> + </connection> + <connection + kind="nios_custom_instruction" + version="9.1" + start="cpu_0.custom_instruction_master" + end="cpu_0_fls_inst.nios_custom_instruction_slave_0"> + <parameter name="CIName" value="fls_inst" /> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="2" /> + </connection> + <connection kind="clock" version="9.1" start="clk_0.clk" end="pio_leds_board.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="pio_leds_board.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x04400040" /> + </connection> + <connection kind="clock" version="9.1" start="clk_0.clk" end="pio_dipswitch.clk" /> + <connection + kind="avalon" + version="6.1" + start="cpu_0.data_master" + end="pio_dipswitch.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x04400060" /> + </connection> + <connection + kind="interrupt" + version="9.1" + start="cpu_0.d_irq" + end="pio_dipswitch.irq"> + <parameter name="irqNumber" value="9" /> + </connection> </system> |