summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorTobias Klauser <tklauser@distanz.ch>2010-03-26 15:25:16 +0100
committerTobias Klauser <klto@zhaw.ch>2010-03-26 15:25:16 +0100
commit82dcb83ed8cd6bfe5d79541a972028b650dc03c3 (patch)
tree6a41c6a90417f8715f928b3342af97e7d14c29b7
Initial commit
Diffstat
-rw-r--r--.gitignore1
-rw-r--r--dionysos_top.vhd235
-rw-r--r--lib/altera/cyc3_pll_0ns.qip5
-rw-r--r--lib/altera/cyc3_pll_0ns.vhd351
-rw-r--r--lib/altera/cyc3_pll_m3ns.qip5
-rw-r--r--lib/altera/cyc3_pll_m3ns.vhd351
-rw-r--r--lib/altera/cyc3pll_eth_phy.qip5
-rw-r--r--lib/altera/sinet_pll.qip5
-rw-r--r--lib/altera/sinet_pll.vhd444
-rw-r--r--lib/misc/components/reset_sync.vhd88
-rw-r--r--quartus/dionysos_nios2mmu.bsf166
-rw-r--r--quartus/dionysos_nios2mmu.qpf30
-rw-r--r--quartus/dionysos_nios2mmu.qsf438
-rw-r--r--quartus/dionysos_nios2mmu.sdc202
-rw-r--r--quartus/dionysos_nios2mmu.sopc566
-rw-r--r--quartus/dionysos_nios2mmu.sopcinfo9792
-rw-r--r--quartus/dionysos_sinet.qsf639
17 files changed, 13323 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..f0fb01b
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+quartus/.sopc_builder
diff --git a/dionysos_top.vhd b/dionysos_top.vhd
new file mode 100644
index 0000000..faa6b65
--- /dev/null
+++ b/dionysos_top.vhd
@@ -0,0 +1,235 @@
+------------------------------------------------------------------
+-- _____ ______ _____ -
+-- |_ _| | ____|/ ____| Institute of Embedded Systems -
+-- | | _ __ | |__ | (___ Zuercher Hochschule fuer -
+-- | | | '_ \| __| \___ \ angewandte Wissenschaften -
+-- _| |_| | | | |____ ____) | (University of Applied Sciences) -
+-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+------------------------------------------------------------------
+-- $LastChangedDate: 2008-02-06 14:28:53 +0100 (Mi, 06 Feb 2008) $
+-- $Rev: 828 $
+-- $Author: ffar $
+-----------------------------------------------------------------
+--
+-- Change History
+-- Date |Name |Modification
+------------|----------|-----------------------------------------
+-- 14.02.07 | kelt |file created for SInet
+------------|----------|-----------------------------------------
+-- 22.02.10 | klto |file adjusted for dionysos-nios2mmu project
+-----------------------------------------------------------------
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library ines_misc;
+ use ines_misc.reset_sync_pkg.all;
+
+--! \brief Top file for design on Dionysos board
+entity dionysos_top is
+ port(
+ --!@name Clock and reset inputs
+ --@{
+ clock_50_i : in std_logic; --! 50 MHz system clock
+ fpga_reset_n_i : in std_logic; --! FPGA reset from voltage monitor
+ --@}
+
+ --!@name Cyclone EPCS config device interface
+ --@{
+ --! \anchor epcs_grp
+ config_ce_n_o : out std_logic; --! Cyclone EPCS config device chip select
+ config_asd0_o : out std_logic; --! Cyclone EPCS config device address
+ config_data0_i : in std_logic; --! Cyclone EPCS config device data
+ config_dclk_o : out std_logic; --! Cyclone EPCS config device clock
+ --@}
+
+ --!@name RS232 for Linux console
+ --@{
+ --! \anchor rs_linux_grp
+ nios_uart_rxd_i : in std_logic; --! Linux console UART Receiver
+ nios_uart_txd_o : out std_logic; --! Linux console UART Transmitter
+ --@}
+
+ --!@name GP-LEDs
+ --@{
+ --! \anchor led_grp
+ gp_led_o : out std_logic_vector(3 downto 0); --! general purpose LEDs
+ gen_led_g_o : out std_logic_vector(6 downto 0); --! green LEDs at front cover
+ gen_led_r_o : out std_logic_vector(6 downto 0); --! red LEDs at front cover
+ --@}
+
+ --!@name DPDT Switch
+ --@{
+ --! \anchor switch_grp
+ switch_i : in std_logic_vector(3 downto 0); --! Dip-Switch[3:0]
+ --@}
+
+ --!@name Reserve Pins
+ --@{
+ reserve0_i : in std_logic; --! unused pin
+ reserve1_i : in std_logic; --! unused pin
+ reserve2_i : in std_logic; --! unused pin
+ reserve3_i : in std_logic; --! unused pin
+ reserve4_i : in std_logic; --! unused pin
+ reserve5_i : in std_logic; --! unused pin
+ reserve6_i : in std_logic; --! unused pin
+ reserve7_i : in std_logic; --! unused pin
+ reserve8_i : in std_logic; --! unused pin
+ --@}
+
+ --!@name SDRAM Interface
+ --@{
+ --! \anchor sdram_grp
+ dram_d_io : inout std_logic_vector(15 downto 0); --! SDRAM Data bus 16 Bits
+ dram_a_o : out std_logic_vector(12 downto 0); --! SDRAM Address bus 12 Bits
+ dram_clk_o : out std_logic; --! SDRAM Clock
+ dram_cke_o : out std_logic; --! SDRAM Clock Enable
+ dram_ldqm_o : out std_logic; --! SDRAM Low-byte Data Mask
+ dram_udqm_o : out std_logic; --! SDRAM High-byte Data Mask
+ dram_we_n_o : out std_logic; --! SDRAM Write Enable
+ dram_cas_n_o : out std_logic; --! SDRAM Column Address Strobe
+ dram_ras_n_o : out std_logic; --! SDRAM Row Address Strobe
+ dram_cs_n_o : out std_logic; --! SDRAM Chip Select
+ dram_ba0_n_o : out std_logic; --! SDRAM Bank Address 0
+ dram_ba1_n_o : out std_logic; --! SDRAM Bank Address 0
+ --@}
+
+ --!@name Flash Interface
+ --@{
+ --! \anchor flash_grp
+ flash_d_io : inout std_logic_vector(7 downto 0); --! FLASH Data bus 8 Bits
+ flash_a_o : out std_logic_vector(21 downto 0); --! FLASH Address bus 22 Bits
+ flash_we_n_o : out std_logic; --! FLASH Write Enable
+ flash_reset_n_o : out std_logic; --! FLASH Reset
+ flash_oe_n_o : out std_logic; --! FLASH Output Enable
+ flash_ce_n_o : out std_logic; --! FLASH Chip Enable
+ fash_acc_o : out std_logic --!
+ --@}
+ );
+end dionysos_top;
+
+architecture rtl of dionysos_top is
+
+ --! FPGA main clock frequency (50MHz)
+ constant C_FPGA_FREQ : integer := 50000000;
+
+ --! 50 MHz Clock which is Source Synchronous to the DRAM Data
+ signal pll_clk_50 : std_logic;
+ --! 25 MHz Clock
+ signal pll_clk_25 : std_logic;
+ --! 12.5 MHz Clock
+ signal pll_clk_12_5 : std_logic;
+ --! main design reset after reset circuit
+ signal reset_n : std_logic;
+ --! synchronous reset
+ signal fpga_reset_n_ff : std_logic;
+ --! Reset for the NIOS. Active in Ethernet Modus (no DSL)
+ signal reset_nios_n : std_logic;
+
+ --! front pannel LEDs
+ signal leds : std_logic_vector(15 downto 0);
+
+ --! @name SDRAM Data
+ --@{
+ --! Nios SDRAM controller data mask (byte select)
+ signal dram_dqm : std_logic_vector(1 downto 0);
+ --! Nios SDRAM controller bank address
+ signal dram_ba : std_logic_vector(1 downto 0);
+ --@}
+
+ --! synchronised on clock dip switch states
+ signal sw_sync : std_logic_vector(switch_i'range);
+
+ begin
+--! @name Components
+--@{
+
+ -- generate ETH-PHY 50MHz clock
+
+ --! PLL to generate all clocks dram clock (shift -3ns)
+ sinet_pll : entity work.sinet_pll
+ port map (
+ inclk0 => clock_50_i, -- 50 MHz in
+ c0 => pll_clk_50, -- 50MHz source synchronous clock out
+ c1 => pll_clk_25, -- 25MHz clock output
+ c2 => pll_clk_12_5, -- 12.5MHz clock output
+ c3 => dram_clk_o -- 50MHz clock output (-3ns)
+ );
+
+ --! synchronize reset
+ reset_n_sync : reset_sync
+ generic map(
+ STAGES => 2
+ )
+ port map(
+ clk_i => pll_clk_50,
+ reset1_n_i => fpga_reset_n_i,
+ reset2_n_i => '1',
+ reset_n_o => fpga_reset_n_ff
+ );
+
+ --! Delay reset => Latch in Time from Power up for the RMII-Phy (min 167ms)
+ reset_gen : reset_sync
+ generic map(
+ STAGES => 10000000 --200ms
+ )
+ port map(
+ clk_i => pll_clk_50,
+ reset1_n_i => fpga_reset_n_ff,
+ reset2_n_i => '1',
+ reset_n_o => reset_n -- reset for all other components
+ );
+
+ -- NIOSII CPU
+ flash_reset_n_o <= '1';
+ fash_acc_o <= '0'; -- Hardware Write Protect input (accelerated program operations)
+ dram_ldqm_o <= dram_dqm(0);
+ dram_udqm_o <= dram_dqm(1);
+ dram_ba0_n_o <= dram_ba(0);
+ dram_ba1_n_o <= dram_ba(1);
+ reset_nios_n <= reset_n;
+
+ --! \brief Altera SOPC-Builder component
+ --! \details
+ --! \li NiosII CPU
+ --! \li SDRAM Interface
+ --! \li Flash Interface
+ --! \li Uart
+ --! \li EPCS Controller
+ --! \n See \subpage nios_config_page for details
+
+ cpu : entity work.cpu_0
+ port map(
+ clk => pll_clk_50,
+ reset_n => reset_nios_n,
+
+ -- the_sdram_0
+ zs_addr_from_the_sdram_0 => dram_a_o(11 downto 0), -- dram_a_o(12) is for 32Mbit SDRAM
+ zs_ba_from_the_sdram_0 => dram_ba,
+ zs_cas_n_from_the_sdram_0 => dram_cas_n_o,
+ zs_cke_from_the_sdram_0 => dram_cke_o,
+ zs_cs_n_from_the_sdram_0 => dram_cs_n_o,
+ zs_dq_to_and_from_the_sdram_0 => dram_d_io,
+ zs_dqm_from_the_sdram_0 => dram_dqm,
+ zs_ras_n_from_the_sdram_0 => dram_ras_n_o,
+ zs_we_n_from_the_sdram_0 => dram_we_n_o,
+
+ -- the_tri_state_bridge_0_avalon_slave
+ select_n_to_the_cfi_flash_0 => flash_ce_n_o,
+ tri_state_bridge_0_address => flash_a_o,
+ tri_state_bridge_0_data => flash_d_io,
+ tri_state_bridge_0_readn => flash_oe_n_o,
+ write_n_to_the_cfi_flash_0 => flash_we_n_o,
+
+ -- the_uart_0
+ rxd_to_the_uart_0 => nios_uart_rxd_i,
+ txd_from_the_uart_0 => nios_uart_txd_o,
+
+ -- the_epcs_controller
+ data0_to_the_epcs_controller => config_data0_i,
+ dclk_from_the_epcs_controller => config_dclk_o,
+ sce_from_the_epcs_controller => config_ce_n_o,
+ sdo_from_the_epcs_controller => config_asd0_o
+ );
+--@}
+end rtl;
diff --git a/lib/altera/cyc3_pll_0ns.qip b/lib/altera/cyc3_pll_0ns.qip
new file mode 100644
index 0000000..b5fc63e
--- /dev/null
+++ b/lib/altera/cyc3_pll_0ns.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "8.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cyc3_pll_0ns.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3_pll_0ns.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3_pll_0ns.ppf"]
diff --git a/lib/altera/cyc3_pll_0ns.vhd b/lib/altera/cyc3_pll_0ns.vhd
new file mode 100644
index 0000000..6ef53f9
--- /dev/null
+++ b/lib/altera/cyc3_pll_0ns.vhd
@@ -0,0 +1,351 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll
+
+-- ============================================================
+-- File Name: cyc3_pll_0ns.vhd
+-- Megafunction Name(s):
+-- altpll
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.0 Build 215 05/29/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY cyc3_pll_0ns IS
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC
+ );
+END cyc3_pll_0ns;
+
+
+ARCHITECTURE SYN OF cyc3_pll_0ns IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+ COMPONENT altpll
+ GENERIC (
+ bandwidth_type : STRING;
+ clk0_divide_by : NATURAL;
+ clk0_duty_cycle : NATURAL;
+ clk0_multiply_by : NATURAL;
+ clk0_phase_shift : STRING;
+ compensate_clock : STRING;
+ inclk0_input_frequency : NATURAL;
+ intended_device_family : STRING;
+ lpm_hint : STRING;
+ lpm_type : STRING;
+ operation_mode : STRING;
+ pll_type : STRING;
+ port_activeclock : STRING;
+ port_areset : STRING;
+ port_clkbad0 : STRING;
+ port_clkbad1 : STRING;
+ port_clkloss : STRING;
+ port_clkswitch : STRING;
+ port_configupdate : STRING;
+ port_fbin : STRING;
+ port_inclk0 : STRING;
+ port_inclk1 : STRING;
+ port_locked : STRING;
+ port_pfdena : STRING;
+ port_phasecounterselect : STRING;
+ port_phasedone : STRING;
+ port_phasestep : STRING;
+ port_phaseupdown : STRING;
+ port_pllena : STRING;
+ port_scanaclr : STRING;
+ port_scanclk : STRING;
+ port_scanclkena : STRING;
+ port_scandata : STRING;
+ port_scandataout : STRING;
+ port_scandone : STRING;
+ port_scanread : STRING;
+ port_scanwrite : STRING;
+ port_clk0 : STRING;
+ port_clk1 : STRING;
+ port_clk2 : STRING;
+ port_clk3 : STRING;
+ port_clk4 : STRING;
+ port_clk5 : STRING;
+ port_clkena0 : STRING;
+ port_clkena1 : STRING;
+ port_clkena2 : STRING;
+ port_clkena3 : STRING;
+ port_clkena4 : STRING;
+ port_clkena5 : STRING;
+ port_extclk0 : STRING;
+ port_extclk1 : STRING;
+ port_extclk2 : STRING;
+ port_extclk3 : STRING;
+ width_clock : NATURAL
+ );
+ PORT (
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ sub_wire4_bv(0 DOWNTO 0) <= "0";
+ sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
+ sub_wire1 <= sub_wire0(0);
+ c0 <= sub_wire1;
+ sub_wire2 <= inclk0;
+ sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+ altpll_component : altpll
+ GENERIC MAP (
+ bandwidth_type => "AUTO",
+ clk0_divide_by => 1,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 1,
+ clk0_phase_shift => "0",
+ compensate_clock => "CLK0",
+ inclk0_input_frequency => 20000,
+ intended_device_family => "Cyclone III",
+ lpm_hint => "CBX_MODULE_PREFIX=cyc3_pll_0ns",
+ lpm_type => "altpll",
+ operation_mode => "NORMAL",
+ pll_type => "Fast",
+ port_activeclock => "PORT_UNUSED",
+ port_areset => "PORT_UNUSED",
+ port_clkbad0 => "PORT_UNUSED",
+ port_clkbad1 => "PORT_UNUSED",
+ port_clkloss => "PORT_UNUSED",
+ port_clkswitch => "PORT_UNUSED",
+ port_configupdate => "PORT_UNUSED",
+ port_fbin => "PORT_UNUSED",
+ port_inclk0 => "PORT_USED",
+ port_inclk1 => "PORT_UNUSED",
+ port_locked => "PORT_UNUSED",
+ port_pfdena => "PORT_UNUSED",
+ port_phasecounterselect => "PORT_UNUSED",
+ port_phasedone => "PORT_UNUSED",
+ port_phasestep => "PORT_UNUSED",
+ port_phaseupdown => "PORT_UNUSED",
+ port_pllena => "PORT_UNUSED",
+ port_scanaclr => "PORT_UNUSED",
+ port_scanclk => "PORT_UNUSED",
+ port_scanclkena => "PORT_UNUSED",
+ port_scandata => "PORT_UNUSED",
+ port_scandataout => "PORT_UNUSED",
+ port_scandone => "PORT_UNUSED",
+ port_scanread => "PORT_UNUSED",
+ port_scanwrite => "PORT_UNUSED",
+ port_clk0 => "PORT_USED",
+ port_clk1 => "PORT_UNUSED",
+ port_clk2 => "PORT_UNUSED",
+ port_clk3 => "PORT_UNUSED",
+ port_clk4 => "PORT_UNUSED",
+ port_clk5 => "PORT_UNUSED",
+ port_clkena0 => "PORT_UNUSED",
+ port_clkena1 => "PORT_UNUSED",
+ port_clkena2 => "PORT_UNUSED",
+ port_clkena3 => "PORT_UNUSED",
+ port_clkena4 => "PORT_UNUSED",
+ port_clkena5 => "PORT_UNUSED",
+ port_extclk0 => "PORT_UNUSED",
+ port_extclk1 => "PORT_UNUSED",
+ port_extclk2 => "PORT_UNUSED",
+ port_extclk3 => "PORT_UNUSED",
+ width_clock => 5
+ )
+ PORT MAP (
+ inclk => sub_wire3,
+ clk => sub_wire0
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "cyc3_pll_0ns.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "Fast"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.vhd TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.ppf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.inc FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.cmp TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.bsf FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns_inst.vhd FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns_waveforms.html TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns_wave*.jpg FALSE FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/lib/altera/cyc3_pll_m3ns.qip b/lib/altera/cyc3_pll_m3ns.qip
new file mode 100644
index 0000000..0a32086
--- /dev/null
+++ b/lib/altera/cyc3_pll_m3ns.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "8.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cyc3_pll_m3ns.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3_pll_m3ns.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3_pll_m3ns.ppf"]
diff --git a/lib/altera/cyc3_pll_m3ns.vhd b/lib/altera/cyc3_pll_m3ns.vhd
new file mode 100644
index 0000000..0643ce0
--- /dev/null
+++ b/lib/altera/cyc3_pll_m3ns.vhd
@@ -0,0 +1,351 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll
+
+-- ============================================================
+-- File Name: cyc3_pll_m3ns.vhd
+-- Megafunction Name(s):
+-- altpll
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.0 Build 215 05/29/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY cyc3_pll_m3ns IS
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC
+ );
+END cyc3_pll_m3ns;
+
+
+ARCHITECTURE SYN OF cyc3_pll_m3ns IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+ COMPONENT altpll
+ GENERIC (
+ bandwidth_type : STRING;
+ clk0_divide_by : NATURAL;
+ clk0_duty_cycle : NATURAL;
+ clk0_multiply_by : NATURAL;
+ clk0_phase_shift : STRING;
+ compensate_clock : STRING;
+ inclk0_input_frequency : NATURAL;
+ intended_device_family : STRING;
+ lpm_hint : STRING;
+ lpm_type : STRING;
+ operation_mode : STRING;
+ pll_type : STRING;
+ port_activeclock : STRING;
+ port_areset : STRING;
+ port_clkbad0 : STRING;
+ port_clkbad1 : STRING;
+ port_clkloss : STRING;
+ port_clkswitch : STRING;
+ port_configupdate : STRING;
+ port_fbin : STRING;
+ port_inclk0 : STRING;
+ port_inclk1 : STRING;
+ port_locked : STRING;
+ port_pfdena : STRING;
+ port_phasecounterselect : STRING;
+ port_phasedone : STRING;
+ port_phasestep : STRING;
+ port_phaseupdown : STRING;
+ port_pllena : STRING;
+ port_scanaclr : STRING;
+ port_scanclk : STRING;
+ port_scanclkena : STRING;
+ port_scandata : STRING;
+ port_scandataout : STRING;
+ port_scandone : STRING;
+ port_scanread : STRING;
+ port_scanwrite : STRING;
+ port_clk0 : STRING;
+ port_clk1 : STRING;
+ port_clk2 : STRING;
+ port_clk3 : STRING;
+ port_clk4 : STRING;
+ port_clk5 : STRING;
+ port_clkena0 : STRING;
+ port_clkena1 : STRING;
+ port_clkena2 : STRING;
+ port_clkena3 : STRING;
+ port_clkena4 : STRING;
+ port_clkena5 : STRING;
+ port_extclk0 : STRING;
+ port_extclk1 : STRING;
+ port_extclk2 : STRING;
+ port_extclk3 : STRING;
+ width_clock : NATURAL
+ );
+ PORT (
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ sub_wire4_bv(0 DOWNTO 0) <= "0";
+ sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
+ sub_wire1 <= sub_wire0(0);
+ c0 <= sub_wire1;
+ sub_wire2 <= inclk0;
+ sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+ altpll_component : altpll
+ GENERIC MAP (
+ bandwidth_type => "AUTO",
+ clk0_divide_by => 1,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 1,
+ clk0_phase_shift => "-3000",
+ compensate_clock => "CLK0",
+ inclk0_input_frequency => 20000,
+ intended_device_family => "Cyclone III",
+ lpm_hint => "CBX_MODULE_PREFIX=cyc3_pll_m3ns",
+ lpm_type => "altpll",
+ operation_mode => "NORMAL",
+ pll_type => "Fast",
+ port_activeclock => "PORT_UNUSED",
+ port_areset => "PORT_UNUSED",
+ port_clkbad0 => "PORT_UNUSED",
+ port_clkbad1 => "PORT_UNUSED",
+ port_clkloss => "PORT_UNUSED",
+ port_clkswitch => "PORT_UNUSED",
+ port_configupdate => "PORT_UNUSED",
+ port_fbin => "PORT_UNUSED",
+ port_inclk0 => "PORT_USED",
+ port_inclk1 => "PORT_UNUSED",
+ port_locked => "PORT_UNUSED",
+ port_pfdena => "PORT_UNUSED",
+ port_phasecounterselect => "PORT_UNUSED",
+ port_phasedone => "PORT_UNUSED",
+ port_phasestep => "PORT_UNUSED",
+ port_phaseupdown => "PORT_UNUSED",
+ port_pllena => "PORT_UNUSED",
+ port_scanaclr => "PORT_UNUSED",
+ port_scanclk => "PORT_UNUSED",
+ port_scanclkena => "PORT_UNUSED",
+ port_scandata => "PORT_UNUSED",
+ port_scandataout => "PORT_UNUSED",
+ port_scandone => "PORT_UNUSED",
+ port_scanread => "PORT_UNUSED",
+ port_scanwrite => "PORT_UNUSED",
+ port_clk0 => "PORT_USED",
+ port_clk1 => "PORT_UNUSED",
+ port_clk2 => "PORT_UNUSED",
+ port_clk3 => "PORT_UNUSED",
+ port_clk4 => "PORT_UNUSED",
+ port_clk5 => "PORT_UNUSED",
+ port_clkena0 => "PORT_UNUSED",
+ port_clkena1 => "PORT_UNUSED",
+ port_clkena2 => "PORT_UNUSED",
+ port_clkena3 => "PORT_UNUSED",
+ port_clkena4 => "PORT_UNUSED",
+ port_clkena5 => "PORT_UNUSED",
+ port_extclk0 => "PORT_UNUSED",
+ port_extclk1 => "PORT_UNUSED",
+ port_extclk2 => "PORT_UNUSED",
+ port_extclk3 => "PORT_UNUSED",
+ width_clock => 5
+ )
+ PORT MAP (
+ inclk => sub_wire3,
+ clk => sub_wire0
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "cyc3_pll_m3ns.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "Fast"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.vhd TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.ppf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.inc FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.cmp TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.bsf FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns_inst.vhd FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns_waveforms.html TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns_wave*.jpg FALSE FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/lib/altera/cyc3pll_eth_phy.qip b/lib/altera/cyc3pll_eth_phy.qip
new file mode 100644
index 0000000..3ec98fd
--- /dev/null
+++ b/lib/altera/cyc3pll_eth_phy.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "8.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cyc3pll_eth_phy.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3pll_eth_phy.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3pll_eth_phy.ppf"]
diff --git a/lib/altera/sinet_pll.qip b/lib/altera/sinet_pll.qip
new file mode 100644
index 0000000..8fc5037
--- /dev/null
+++ b/lib/altera/sinet_pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "8.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sinet_pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinet_pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinet_pll.ppf"]
diff --git a/lib/altera/sinet_pll.vhd b/lib/altera/sinet_pll.vhd
new file mode 100644
index 0000000..a9c3abf
--- /dev/null
+++ b/lib/altera/sinet_pll.vhd
@@ -0,0 +1,444 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll
+
+-- ============================================================
+-- File Name: sinet_pll.vhd
+-- Megafunction Name(s):
+-- altpll
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.0 Build 215 05/29/2008 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sinet_pll IS
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC ;
+ c2 : OUT STD_LOGIC ;
+ c3 : OUT STD_LOGIC
+ );
+END sinet_pll;
+
+
+ARCHITECTURE SYN OF sinet_pll IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC ;
+ SIGNAL sub_wire4 : STD_LOGIC ;
+ SIGNAL sub_wire5 : STD_LOGIC ;
+ SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+ COMPONENT altpll
+ GENERIC (
+ bandwidth_type : STRING;
+ clk0_divide_by : NATURAL;
+ clk0_duty_cycle : NATURAL;
+ clk0_multiply_by : NATURAL;
+ clk0_phase_shift : STRING;
+ clk1_divide_by : NATURAL;
+ clk1_duty_cycle : NATURAL;
+ clk1_multiply_by : NATURAL;
+ clk1_phase_shift : STRING;
+ clk2_divide_by : NATURAL;
+ clk2_duty_cycle : NATURAL;
+ clk2_multiply_by : NATURAL;
+ clk2_phase_shift : STRING;
+ clk3_divide_by : NATURAL;
+ clk3_duty_cycle : NATURAL;
+ clk3_multiply_by : NATURAL;
+ clk3_phase_shift : STRING;
+ compensate_clock : STRING;
+ inclk0_input_frequency : NATURAL;
+ intended_device_family : STRING;
+ lpm_hint : STRING;
+ lpm_type : STRING;
+ operation_mode : STRING;
+ pll_type : STRING;
+ port_activeclock : STRING;
+ port_areset : STRING;
+ port_clkbad0 : STRING;
+ port_clkbad1 : STRING;
+ port_clkloss : STRING;
+ port_clkswitch : STRING;
+ port_configupdate : STRING;
+ port_fbin : STRING;
+ port_inclk0 : STRING;
+ port_inclk1 : STRING;
+ port_locked : STRING;
+ port_pfdena : STRING;
+ port_phasecounterselect : STRING;
+ port_phasedone : STRING;
+ port_phasestep : STRING;
+ port_phaseupdown : STRING;
+ port_pllena : STRING;
+ port_scanaclr : STRING;
+ port_scanclk : STRING;
+ port_scanclkena : STRING;
+ port_scandata : STRING;
+ port_scandataout : STRING;
+ port_scandone : STRING;
+ port_scanread : STRING;
+ port_scanwrite : STRING;
+ port_clk0 : STRING;
+ port_clk1 : STRING;
+ port_clk2 : STRING;
+ port_clk3 : STRING;
+ port_clk4 : STRING;
+ port_clk5 : STRING;
+ port_clkena0 : STRING;
+ port_clkena1 : STRING;
+ port_clkena2 : STRING;
+ port_clkena3 : STRING;
+ port_clkena4 : STRING;
+ port_clkena5 : STRING;
+ port_extclk0 : STRING;
+ port_extclk1 : STRING;
+ port_extclk2 : STRING;
+ port_extclk3 : STRING;
+ width_clock : NATURAL
+ );
+ PORT (
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ sub_wire7_bv(0 DOWNTO 0) <= "0";
+ sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
+ sub_wire4 <= sub_wire0(3);
+ sub_wire3 <= sub_wire0(2);
+ sub_wire2 <= sub_wire0(1);
+ sub_wire1 <= sub_wire0(0);
+ c0 <= sub_wire1;
+ c1 <= sub_wire2;
+ c2 <= sub_wire3;
+ c3 <= sub_wire4;
+ sub_wire5 <= inclk0;
+ sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+ altpll_component : altpll
+ GENERIC MAP (
+ bandwidth_type => "AUTO",
+ clk0_divide_by => 1,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 1,
+ clk0_phase_shift => "0",
+ clk1_divide_by => 2,
+ clk1_duty_cycle => 50,
+ clk1_multiply_by => 1,
+ clk1_phase_shift => "0",
+ clk2_divide_by => 4,
+ clk2_duty_cycle => 50,
+ clk2_multiply_by => 1,
+ clk2_phase_shift => "0",
+ clk3_divide_by => 1,
+ clk3_duty_cycle => 50,
+ clk3_multiply_by => 1,
+ clk3_phase_shift => "-3000",
+ compensate_clock => "CLK0",
+ inclk0_input_frequency => 20000,
+ intended_device_family => "Cyclone III",
+ lpm_hint => "CBX_MODULE_PREFIX=sinet_pll",
+ lpm_type => "altpll",
+ operation_mode => "NORMAL",
+ pll_type => "Fast",
+ port_activeclock => "PORT_UNUSED",
+ port_areset => "PORT_UNUSED",
+ port_clkbad0 => "PORT_UNUSED",
+ port_clkbad1 => "PORT_UNUSED",
+ port_clkloss => "PORT_UNUSED",
+ port_clkswitch => "PORT_UNUSED",
+ port_configupdate => "PORT_UNUSED",
+ port_fbin => "PORT_UNUSED",
+ port_inclk0 => "PORT_USED",
+ port_inclk1 => "PORT_UNUSED",
+ port_locked => "PORT_UNUSED",
+ port_pfdena => "PORT_UNUSED",
+ port_phasecounterselect => "PORT_UNUSED",
+ port_phasedone => "PORT_UNUSED",
+ port_phasestep => "PORT_UNUSED",
+ port_phaseupdown => "PORT_UNUSED",
+ port_pllena => "PORT_UNUSED",
+ port_scanaclr => "PORT_UNUSED",
+ port_scanclk => "PORT_UNUSED",
+ port_scanclkena => "PORT_UNUSED",
+ port_scandata => "PORT_UNUSED",
+ port_scandataout => "PORT_UNUSED",
+ port_scandone => "PORT_UNUSED",
+ port_scanread => "PORT_UNUSED",
+ port_scanwrite => "PORT_UNUSED",
+ port_clk0 => "PORT_USED",
+ port_clk1 => "PORT_USED",
+ port_clk2 => "PORT_USED",
+ port_clk3 => "PORT_USED",
+ port_clk4 => "PORT_UNUSED",
+ port_clk5 => "PORT_UNUSED",
+ port_clkena0 => "PORT_UNUSED",
+ port_clkena1 => "PORT_UNUSED",
+ port_clkena2 => "PORT_UNUSED",
+ port_clkena3 => "PORT_UNUSED",
+ port_clkena4 => "PORT_UNUSED",
+ port_clkena5 => "PORT_UNUSED",
+ port_extclk0 => "PORT_UNUSED",
+ port_extclk1 => "PORT_UNUSED",
+ port_extclk2 => "PORT_UNUSED",
+ port_extclk3 => "PORT_UNUSED",
+ width_clock => 5
+ )
+ PORT MAP (
+ inclk => sub_wire6,
+ clk => sub_wire0
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-3.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "sinet_pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-3000"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "Fast"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.vhd TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.ppf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.inc FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.cmp TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.bsf FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll_inst.vhd FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll_waveforms.html TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll_wave*.jpg FALSE FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/lib/misc/components/reset_sync.vhd b/lib/misc/components/reset_sync.vhd
new file mode 100644
index 0000000..27c1e78
--- /dev/null
+++ b/lib/misc/components/reset_sync.vhd
@@ -0,0 +1,88 @@
+------------------------------------------------------------------
+-- _____ ______ _____ -
+-- |_ _| | ____|/ ____| Institute of Embedded Systems -
+-- | | _ __ | |__ | (___ Zuercher Hochschule fuer -
+-- | | | '_ \| __| \___ \ angewandte Wissenschaften -
+-- _| |_| | | | |____ ____) | (University of Applied Sciences) -
+-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+------------------------------------------------------------------
+--
+-- Project : SInet
+-- Module : synthesis library ines_misc
+-- Description : reset synchronisytion
+--
+-- $LastChangedDate: 2008-10-31 12:06:00 +0100 (Fri, 31 Oct 2008) $
+-- $Rev: 1905 $
+-- $Author: ffar $
+-----------------------------------------------------------------
+--
+-- Change History
+-- Date |Name |Modification
+-----------------------------------------------------------------
+-- 02.11.07 | ffar | file created based on library component
+-- 24.06.08 | kelt | resets synchronized
+-----------------------------------------------------------------
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+package reset_sync_pkg is
+ component reset_sync
+ generic(
+ STAGES : integer := 4
+ );
+ port(
+ clk_i : in std_logic;
+ reset1_n_i : in std_logic;
+ reset2_n_i : in std_logic := '1';
+ reset_n_o : out std_logic := '0'
+ );
+ end component reset_sync;
+end package reset_sync_pkg;
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+entity reset_sync is
+ generic(
+ STAGES : integer := 4
+ );
+ port(
+ clk_i : in std_logic;
+ reset1_n_i : in std_logic;
+ reset2_n_i : in std_logic := '1';
+ reset_n_o : out std_logic := '0'
+ );
+end reset_sync;
+
+architecture rtl of reset_sync is
+
+ signal reset1_n_f, reset1_n_ff : std_logic;
+ signal reset2_n_f, reset2_n_ff : std_logic;
+
+begin
+
+ reset_prc : process(clk_i)
+ variable count : integer range 0 to STAGES-1 := 0;
+ begin
+ if clk_i'event and clk_i = '1' then
+ reset1_n_f <= reset1_n_i;
+ reset1_n_ff <= reset1_n_f;
+ reset2_n_f <= reset2_n_i;
+ reset2_n_ff <= reset2_n_f;
+ if (reset1_n_ff and reset2_n_ff) = '0' then
+ reset_n_o <= '0';
+ count := 0;
+ elsif count < STAGES-1 then
+ reset_n_o <= '0';
+ count := count + 1;
+ else
+ reset_n_o <= '1';
+ end if;
+ end if;
+ end process reset_prc;
+
+end rtl; \ No newline at end of file
diff --git a/quartus/dionysos_nios2mmu.bsf b/quartus/dionysos_nios2mmu.bsf
new file mode 100644
index 0000000..fb0209d
--- /dev/null
+++ b/quartus/dionysos_nios2mmu.bsf
@@ -0,0 +1,166 @@
+(header "symbol" (version "1.1"))
+(symbol
+(rect 0 0 448 432)
+(text "dionysos_nios2mmu" (rect 4 0 136 16)(font "Arial" (font_size 10)))
+(text "inst" (rect 4 416 28 432)(font "Arial"))
+(port
+(pt 0 32)
+(input)
+(text "clk_0 " (rect 0 0 25 16)(font "Arial" (font_size 8)))
+(text "clk_0 " (rect 20 25 45 41)(font "Arial" (font_size 8)))
+(line (pt 0 32)(pt 16 32)(line_width 1))
+)
+(port
+(pt 0 48)
+(input)
+(text "reset_n " (rect 0 0 36 16)(font "Arial" (font_size 8)))
+(text "reset_n " (rect 20 41 56 57)(font "Arial" (font_size 8)))
+(line (pt 0 48)(pt 16 48)(line_width 1))
+)
+(port
+(pt 0 80)
+(input)
+(text "data0_to_the_epcs_flash_controller_0 " (rect 0 0 184 16)(font "Arial" (font_size 8)))
+(text "data0_to_the_epcs_flash_controller_0 " (rect 20 73 204 89)(font "Arial" (font_size 8)))
+(line (pt 0 80)(pt 16 80)(line_width 1))
+)
+(port
+(pt 0 400)
+(input)
+(text "rxd_to_the_uart_0 " (rect 0 0 87 16)(font "Arial" (font_size 8)))
+(text "rxd_to_the_uart_0 " (rect 20 393 107 409)(font "Arial" (font_size 8)))
+(line (pt 0 400)(pt 16 400)(line_width 1))
+)
+(port
+(pt 448 80)
+(output)
+(text "dclk_from_the_epcs_flash_controller_0 " (rect 0 0 188 16)(font "Arial" (font_size 8)))
+(text "dclk_from_the_epcs_flash_controller_0 " (rect 233 73 421 89)(font "Arial" (font_size 8)))
+(line (pt 432 80)(pt 448 80)(line_width 1))
+)
+(port
+(pt 448 96)
+(output)
+(text "sce_from_the_epcs_flash_controller_0 " (rect 0 0 186 16)(font "Arial" (font_size 8)))
+(text "sce_from_the_epcs_flash_controller_0 " (rect 235 89 421 105)(font "Arial" (font_size 8)))
+(line (pt 432 96)(pt 448 96)(line_width 1))
+)
+(port
+(pt 448 112)
+(output)
+(text "sdo_from_the_epcs_flash_controller_0 " (rect 0 0 186 16)(font "Arial" (font_size 8)))
+(text "sdo_from_the_epcs_flash_controller_0 " (rect 234 105 421 121)(font "Arial" (font_size 8)))
+(line (pt 432 112)(pt 448 112)(line_width 1))
+)
+(port
+(pt 448 144)
+(output)
+(text "zs_addr_from_the_sdram_0[11..0] " (rect 0 0 165 16)(font "Arial" (font_size 8)))
+(text "zs_addr_from_the_sdram_0[11..0] " (rect 255 137 421 153)(font "Arial" (font_size 8)))
+(line (pt 432 144)(pt 448 144)(line_width 3))
+)
+(port
+(pt 448 160)
+(output)
+(text "zs_ba_from_the_sdram_0[1..0] " (rect 0 0 150 16)(font "Arial" (font_size 8)))
+(text "zs_ba_from_the_sdram_0[1..0] " (rect 271 153 421 169)(font "Arial" (font_size 8)))
+(line (pt 432 160)(pt 448 160)(line_width 3))
+)
+(port
+(pt 448 176)
+(output)
+(text "zs_cas_n_from_the_sdram_0 " (rect 0 0 143 16)(font "Arial" (font_size 8)))
+(text "zs_cas_n_from_the_sdram_0 " (rect 278 169 421 185)(font "Arial" (font_size 8)))
+(line (pt 432 176)(pt 448 176)(line_width 1))
+)
+(port
+(pt 448 192)
+(output)
+(text "zs_cke_from_the_sdram_0 " (rect 0 0 131 16)(font "Arial" (font_size 8)))
+(text "zs_cke_from_the_sdram_0 " (rect 290 185 421 201)(font "Arial" (font_size 8)))
+(line (pt 432 192)(pt 448 192)(line_width 1))
+)
+(port
+(pt 448 208)
+(output)
+(text "zs_cs_n_from_the_sdram_0 " (rect 0 0 137 16)(font "Arial" (font_size 8)))
+(text "zs_cs_n_from_the_sdram_0 " (rect 284 201 421 217)(font "Arial" (font_size 8)))
+(line (pt 432 208)(pt 448 208)(line_width 1))
+)
+(port
+(pt 448 224)
+(bidir)
+(text "zs_dq_to_and_from_the_sdram_0[15..0] " (rect 0 0 195 16)(font "Arial" (font_size 8)))
+(text "zs_dq_to_and_from_the_sdram_0[15..0] " (rect 226 217 421 233)(font "Arial" (font_size 8)))
+(line (pt 432 224)(pt 448 224)(line_width 3))
+)
+(port
+(pt 448 240)
+(output)
+(text "zs_dqm_from_the_sdram_0[1..0] " (rect 0 0 159 16)(font "Arial" (font_size 8)))
+(text "zs_dqm_from_the_sdram_0[1..0] " (rect 262 233 421 249)(font "Arial" (font_size 8)))
+(line (pt 432 240)(pt 448 240)(line_width 3))
+)
+(port
+(pt 448 256)
+(output)
+(text "zs_ras_n_from_the_sdram_0 " (rect 0 0 141 16)(font "Arial" (font_size 8)))
+(text "zs_ras_n_from_the_sdram_0 " (rect 280 249 421 265)(font "Arial" (font_size 8)))
+(line (pt 432 256)(pt 448 256)(line_width 1))
+)
+(port
+(pt 448 272)
+(output)
+(text "zs_we_n_from_the_sdram_0 " (rect 0 0 139 16)(font "Arial" (font_size 8)))
+(text "zs_we_n_from_the_sdram_0 " (rect 282 265 421 281)(font "Arial" (font_size 8)))
+(line (pt 432 272)(pt 448 272)(line_width 1))
+)
+(port
+(pt 448 304)
+(output)
+(text "select_n_to_the_cfi_flash_0 " (rect 0 0 134 16)(font "Arial" (font_size 8)))
+(text "select_n_to_the_cfi_flash_0 " (rect 287 297 421 313)(font "Arial" (font_size 8)))
+(line (pt 432 304)(pt 448 304)(line_width 1))
+)
+(port
+(pt 448 320)
+(output)
+(text "tri_state_bridge_0_address[21..0] " (rect 0 0 163 16)(font "Arial" (font_size 8)))
+(text "tri_state_bridge_0_address[21..0] " (rect 257 313 421 329)(font "Arial" (font_size 8)))
+(line (pt 432 320)(pt 448 320)(line_width 3))
+)
+(port
+(pt 448 336)
+(bidir)
+(text "tri_state_bridge_0_data[7..0] " (rect 0 0 139 16)(font "Arial" (font_size 8)))
+(text "tri_state_bridge_0_data[7..0] " (rect 282 329 421 345)(font "Arial" (font_size 8)))
+(line (pt 432 336)(pt 448 336)(line_width 3))
+)
+(port
+(pt 448 352)
+(output)
+(text "tri_state_bridge_0_readn " (rect 0 0 122 16)(font "Arial" (font_size 8)))
+(text "tri_state_bridge_0_readn " (rect 299 345 421 361)(font "Arial" (font_size 8)))
+(line (pt 432 352)(pt 448 352)(line_width 1))
+)
+(port
+(pt 448 368)
+(output)
+(text "write_n_to_the_cfi_flash_0 " (rect 0 0 128 16)(font "Arial" (font_size 8)))
+(text "write_n_to_the_cfi_flash_0 " (rect 292 361 421 377)(font "Arial" (font_size 8)))
+(line (pt 432 368)(pt 448 368)(line_width 1))
+)
+(port
+(pt 448 400)
+(output)
+(text "txd_from_the_uart_0 " (rect 0 0 98 16)(font "Arial" (font_size 8)))
+(text "txd_from_the_uart_0 " (rect 322 393 421 409)(font "Arial" (font_size 8)))
+(line (pt 432 400)(pt 448 400)(line_width 1))
+)
+(drawing
+(line (pt 16 64)(pt 431 64)(color 0 0 0)(dotted)(line_width 1))
+(line (pt 16 128)(pt 431 128)(color 0 0 0)(dotted)(line_width 1))
+(line (pt 16 288)(pt 431 288)(color 0 0 0)(dotted)(line_width 1))
+(line (pt 16 384)(pt 431 384)(color 0 0 0)(dotted)(line_width 1))
+(rectangle (rect 16 16 432 416)(line_width 1)))
+)
diff --git a/quartus/dionysos_nios2mmu.qpf b/quartus/dionysos_nios2mmu.qpf
new file mode 100644
index 0000000..f89d952
--- /dev/null
+++ b/quartus/dionysos_nios2mmu.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 9.1 Build 222 10/21/2009 SJ Full Version
+# Date created = 17:15:51 February 22, 2010
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.1"
+DATE = "17:15:51 February 22, 2010"
+
+# Revisions
+
+PROJECT_REVISION = "dionysos_nios2mmu"
diff --git a/quartus/dionysos_nios2mmu.qsf b/quartus/dionysos_nios2mmu.qsf
new file mode 100644
index 0000000..6f7f6be
--- /dev/null
+++ b/quartus/dionysos_nios2mmu.qsf
@@ -0,0 +1,438 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 9.1 Build 222 10/21/2009 SJ Full Version
+# Date created = 17:15:51 February 22, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# dionysos-nios2mmu_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Device assignments
+# ------------------
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C40F484C6
+
+# Project wide assignments
+# ------------------------
+set_global_assignment -name TOP_LEVEL_ENTITY "dionysos-nios2mmu"
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:15:51 FEBRUARY 22, 2010"
+set_global_assignment -name LAST_QUARTUS_VERSION 9.1
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+
+# Clock inputs
+# ------------
+set_location_assignment PIN_G2 -to clock_50_i
+#set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i
+#set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i
+#set_location_assignment PIN_G21 -to usb_clk_i
+#set_location_assignment PIN_G22 -to sdfe_clk_20mhz_i
+#set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i
+#set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i
+set_location_assignment PIN_A12 -to aux_clk_n_i
+set_location_assignment PIN_B12 -to aux_clk_p_i
+#set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i
+#set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i
+#set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i
+#set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i
+
+# FPGA programming pins
+# ---------------------
+set_location_assignment PIN_E2 -to config_ce_n_o
+set_location_assignment PIN_D1 -to config_asd0_o
+set_location_assignment PIN_K1 -to config_data0_i
+set_location_assignment PIN_K2 -to config_dclk_o
+
+# FPGA bank 1
+# -------------
+set_location_assignment PIN_G4 -to nios_uart_txd_o
+set_location_assignment PIN_B2 -to nios_uart_rxd_i
+#set_location_assignment PIN_G3 -to mstt_uart_txd_o
+#set_location_assignment PIN_B1 -to mstt_uart_rxd_i
+set_location_assignment PIN_G5 -to gen_led_r_o[5]
+set_location_assignment PIN_E4 -to gen_led_g_o[5]
+set_location_assignment PIN_E3 -to iom_du_o
+set_location_assignment PIN_C2 -to iom_dd_i
+set_location_assignment PIN_C1 -to iom_fsc_o
+set_location_assignment PIN_D2 -to iom_dclk_o
+set_location_assignment PIN_H7 -to reserve0_i
+set_location_assignment PIN_J6 -to reserve1_i
+#set_location_assignment PIN_E1 -to i2c_sda_io
+#set_location_assignment PIN_F2 -to i2c_scl_o
+set_location_assignment PIN_F1 -to gen_led_r_o[4]
+set_location_assignment PIN_H8 -to gen_led_g_o[4]
+set_location_assignment PIN_J5 -to switch_i[0]
+set_location_assignment PIN_H5 -to switch_i[1]
+set_location_assignment PIN_L8 -to switch_i[2]
+set_location_assignment PIN_K8 -to switch_i[3]
+set_location_assignment PIN_K7 -to gen_led_r_o[0]
+set_location_assignment PIN_J4 -to gen_led_g_o[0]
+set_location_assignment PIN_H2 -to gp_led_o[0]
+set_location_assignment PIN_H1 -to gp_led_o[1]
+set_location_assignment PIN_J3 -to gp_led_o[2]
+set_location_assignment PIN_J2 -to gp_led_o[3]
+
+# FPGA bank 2
+# -----------
+#set_location_assignment PIN_L6 -to ssram_d_io[2]
+#set_location_assignment PIN_M6 -to ssram_a_o[17]
+#set_location_assignment PIN_M2 -to ssram_bwc_n_o
+#set_location_assignment PIN_M1 -to ssram_bwb_n_o
+#set_location_assignment PIN_M4 -to ssram_ce_n_o
+#set_location_assignment PIN_M3 -to ssram_bwd_n_o
+#set_location_assignment PIN_N2 -to ssram_a_o[14]
+#set_location_assignment PIN_N1 -to ssram_a_o[13]
+#set_location_assignment PIN_L7 -to ssram_d_io[3]
+#set_location_assignment PIN_M5 -to ssram_a_o[16]
+#set_location_assignment PIN_P2 -to ssram_d_io[12]
+#set_location_assignment PIN_P1 -to ssram_d_io[11]
+#set_location_assignment PIN_R2 -to ssram_a_o[12]
+#set_location_assignment PIN_R1 -to ssram_a_o[11]
+#set_location_assignment PIN_N5 -to ssram_a_o[15]
+#set_location_assignment PIN_P4 -to ssram_d_io[14]
+#set_location_assignment PIN_P3 -to ssram_d_io[13]
+#set_location_assignment PIN_U2 -to ssram_a_o[6]
+#set_location_assignment PIN_U1 -to ssram_a_o[0]
+#set_location_assignment PIN_V2 -to ssram_a_o[4]
+#set_location_assignment PIN_V1 -to ssram_a_o[3]
+#set_location_assignment PIN_P5 -to ssram_d_io[15]
+#set_location_assignment PIN_N6 -to ssram_oe_n_o
+#set_location_assignment PIN_M7 -to ssram_d_io[0]
+#set_location_assignment PIN_M8 -to ssram_d_io[1]
+#set_location_assignment PIN_N8 -to ssram_bwa_n_o
+#set_location_assignment PIN_W2 -to ssram_a_o[2]
+#set_location_assignment PIN_W1 -to ssram_d_io[16]
+#set_location_assignment PIN_Y2 -to ssram_d_io[7]
+#set_location_assignment PIN_Y1 -to ssram_d_io[6]
+#set_location_assignment PIN_T3 -to ssram_a_o[7]
+#set_location_assignment PIN_N7 -to ssram_we_n_o
+#set_location_assignment PIN_P7 -to ssram_a_o[18]
+#set_location_assignment PIN_AA2 -to ssram_d_io[5]
+#set_location_assignment PIN_AA1 -to ssram_d_io[4]
+#set_location_assignment PIN_V4 -to ssram_a_o[1]
+#set_location_assignment PIN_V3 -to ssram_a_o[5]
+#set_location_assignment PIN_P6 -to ssram_d_io[17]
+#set_location_assignment PIN_T5 -to ssram_a_o[9]
+#set_location_assignment PIN_T4 -to ssram_a_o[8]
+#set_location_assignment PIN_R5 -to ssram_d_io[8]
+#set_location_assignment PIN_R6 -to ssram_d_io[9]
+#set_location_assignment PIN_R7 -to ssram_d_io[10]
+#set_location_assignment PIN_T7 -to ssram_a_o[10]
+
+# FPGA bank 3
+# -----------
+#set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i
+#set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i
+#set_location_assignment PIN_U8 -to et_phy1_crs_1_i
+#set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0]
+#set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1]
+#set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2]
+#set_location_assignment PIN_AA3 -to ssram_clk_o
+set_location_assignment PIN_AB3 -to reserve7_i
+#set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3]
+#set_location_assignment PIN_V7 -to et_phy1_col_1_i
+#set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o
+#set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0]
+#set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1]
+#set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2]
+#set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3]
+#set_location_assignment PIN_W7 -to et_phy1_int_1_i
+set_location_assignment PIN_Y7 -to reserve2_i
+#set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i
+#set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i
+#set_location_assignment PIN_W8 -to et_phy1_crs_2_i
+#set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0]
+#set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1]
+#set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2]
+#set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3]
+#set_location_assignment PIN_T11 -to et_phy1_col_2_i
+set_location_assignment PIN_V9 -to reserve3_i
+set_location_assignment PIN_V10 -to et_phy1_tx_en_2_o
+set_location_assignment PIN_U10 -to et_phy1_txd_2_o[0]
+set_location_assignment PIN_AA8 -to et_phy1_txd_2_o[1]
+set_location_assignment PIN_AB8 -to et_phy1_txd_2_o[2]
+set_location_assignment PIN_AA9 -to et_phy1_txd_2_o[3]
+set_location_assignment PIN_AB9 -to et_phy1_int_2_i
+set_location_assignment PIN_U11 -to et_phy1_mdc_o
+set_location_assignment PIN_V11 -to et_phy1_mdio_io
+#set_location_assignment PIN_W10 -to rst_et_phy1_n_o
+set_location_assignment PIN_Y10 -to gen_led_r_o[3]
+set_location_assignment PIN_AA10 -to gen_led_g_o[3]
+
+# FPGA bank 4
+# -----------
+#set_location_assignment PIN_AA13 -to otg_d_io[0]
+#set_location_assignment PIN_AB13 -to otg_d_io[1]
+#set_location_assignment PIN_AA14 -to otg_d_io[2]
+#set_location_assignment PIN_AB14 -to otg_d_io[3]
+#set_location_assignment PIN_V12 -to otg_d_io[4]
+#set_location_assignment PIN_W13 -to otg_d_io[5]
+#set_location_assignment PIN_Y13 -to otg_d_io[6]
+#set_location_assignment PIN_AA15 -to otg_d_io[7]
+#set_location_assignment PIN_AB15 -to otg_d_io[8]
+#set_location_assignment PIN_U12 -to otg_d_io[9]
+#set_location_assignment PIN_AA16 -to otg_d_io[10]
+#set_location_assignment PIN_AB16 -to otg_d_io[11]
+#set_location_assignment PIN_T12 -to otg_d_io[12]
+#set_location_assignment PIN_T13 -to otg_d_io[13]
+#set_location_assignment PIN_V13 -to otg_d_io[14]
+#set_location_assignment PIN_W14 -to otg_d_io[15]
+#set_location_assignment PIN_U13 -to otg_a_o[0]
+#set_location_assignment PIN_V14 -to otg_a_o[1]
+#set_location_assignment PIN_U14 -to otg_cs_n_o
+#set_location_assignment PIN_U15 -to otg_we_n_o
+#set_location_assignment PIN_V15 -to otg_oe_n_o
+#set_location_assignment PIN_W15 -to otg_int0_i
+#set_location_assignment PIN_T14 -to otg_int1_i
+#set_location_assignment PIN_T15 -to otg_reset_n_o
+#set_location_assignment PIN_AB18 -to otg_dreq0_i
+#set_location_assignment PIN_AA17 -to otg_dreq1_i
+#set_location_assignment PIN_AB17 -to otg_dack0_n_o
+#set_location_assignment PIN_AA18 -to otg_dack1_n_o
+#set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i
+set_location_assignment PIN_W17 -to gen_led_r_o[6]
+#set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o
+set_location_assignment PIN_AB20 -to gen_led_r_o[2]
+set_location_assignment PIN_V16 -to gen_led_g_o[2]
+set_location_assignment PIN_U16 -to reserve4_i
+set_location_assignment PIN_U17 -to reserve5_i
+set_location_assignment PIN_T16 -to aux_clk_p_o
+set_location_assignment PIN_R16 -to aux_clk_n_o
+set_location_assignment PIN_R15 -to gen_led_g_o[6]
+
+# FPGA bank 5
+# -----------
+#set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3]
+#set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2]
+#set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1]
+#set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0]
+#set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3]
+#set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2]
+#set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1]
+#set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0]
+#set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3]
+#set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2]
+#set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1]
+#set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0]
+#set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3]
+#set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2]
+#set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1]
+#set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0]
+#set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i
+#set_location_assignment PIN_V21 -to et_phy2_crs_2_i
+#set_location_assignment PIN_R20 -to rst_et_phy2_n_o
+#set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i
+#set_location_assignment PIN_U21 -to et_phy2_col_2_i
+#set_location_assignment PIN_R18 -to et_phy2_crs_1_i
+#set_location_assignment PIN_R19 -to et_phy2_col_1_i
+#set_location_assignment PIN_N16 -to mpd_io[0]
+#set_location_assignment PIN_R22 -to mpd_io[1]
+#set_location_assignment PIN_R21 -to mpd_io[2]
+#set_location_assignment PIN_P20 -to mpd_io[3]
+#set_location_assignment PIN_P22 -to mpd_io[4]
+#set_location_assignment PIN_P21 -to mpd_io[5]
+#set_location_assignment PIN_N20 -to mpd_io[6]
+#set_location_assignment PIN_N19 -to mpd_io[7]
+set_location_assignment PIN_N18 -to reserve6_i
+set_location_assignment PIN_N21 -to fpga_reset_n_i
+#set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i
+#set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o
+#set_location_assignment PIN_AA20 -to et_phy2_int_1_i
+#set_location_assignment PIN_M20 -to et_phy2_int_2_i
+#set_location_assignment PIN_M19 -to et_phy2_mdc_o
+#set_location_assignment PIN_M16 -to et_phy2_mdio_io
+
+# FPGA bank 6
+# -----------
+set_location_assignment PIN_L22 -to flash_a_o[2]
+set_location_assignment PIN_L21 -to flash_a_o[4]
+set_location_assignment PIN_K19 -to fash_acc_o
+set_location_assignment PIN_K22 -to flash_a_o[6]
+set_location_assignment PIN_K21 -to flash_a_o[18]
+set_location_assignment PIN_J22 -to flash_a_o[12]
+set_location_assignment PIN_J21 -to flash_a_o[14]
+set_location_assignment PIN_H22 -to flash_a_o[13]
+set_location_assignment PIN_H21 -to flash_a_o[11]
+set_location_assignment PIN_K17 -to flash_a_o[9]
+set_location_assignment PIN_K18 -to flash_we_n_o
+set_location_assignment PIN_J18 -to flash_a_o[16]
+set_location_assignment PIN_F22 -to flash_oe_n_o
+set_location_assignment PIN_F21 -to flash_d_io[1]
+set_location_assignment PIN_H20 -to flash_a_o[8]
+set_location_assignment PIN_H19 -to flash_reset_n_o
+set_location_assignment PIN_E22 -to flash_a_o[10]
+set_location_assignment PIN_E21 -to flash_a_o[20]
+set_location_assignment PIN_H18 -to flash_a_o[7]
+set_location_assignment PIN_J17 -to flash_a_o[15]
+set_location_assignment PIN_H16 -to flash_a_o[3]
+set_location_assignment PIN_D22 -to flash_a_o[17]
+set_location_assignment PIN_D21 -to flash_a_o[19]
+set_location_assignment PIN_F20 -to flash_d_io[3]
+set_location_assignment PIN_F19 -to flash_d_io[4]
+set_location_assignment PIN_G18 -to flash_a_o[1]
+set_location_assignment PIN_H17 -to flash_a_o[5]
+set_location_assignment PIN_C22 -to flash_d_io[5]
+set_location_assignment PIN_C21 -to flash_a_o[21]
+set_location_assignment PIN_B22 -to flash_d_io[0]
+set_location_assignment PIN_B21 -to flash_a_o[0]
+set_location_assignment PIN_C20 -to flash_d_io[2]
+set_location_assignment PIN_D20 -to flash_d_io[7]
+set_location_assignment PIN_F17 -to flash_d_io[6]
+set_location_assignment PIN_G17 -to flash_ce_n_o
+
+# FPGA bank 7
+# -----------
+set_location_assignment PIN_F16 -to dram_a_o[0]
+set_location_assignment PIN_E16 -to dram_a_o[1]
+set_location_assignment PIN_F15 -to dram_a_o[2]
+set_location_assignment PIN_G16 -to dram_a_o[3]
+set_location_assignment PIN_G15 -to dram_a_o[4]
+set_location_assignment PIN_F14 -to dram_a_o[5]
+set_location_assignment PIN_H15 -to dram_a_o[6]
+set_location_assignment PIN_H14 -to dram_a_o[7]
+set_location_assignment PIN_D17 -to dram_a_o[8]
+set_location_assignment PIN_C19 -to dram_a_o[9]
+set_location_assignment PIN_D19 -to dram_a_o[10]
+set_location_assignment PIN_A20 -to dram_a_o[11]
+set_location_assignment PIN_B20 -to dram_clk_o
+set_location_assignment PIN_C17 -to dram_d_io[0]
+set_location_assignment PIN_B19 -to dram_d_io[1]
+set_location_assignment PIN_A19 -to dram_d_io[2]
+set_location_assignment PIN_A18 -to dram_d_io[3]
+set_location_assignment PIN_B18 -to dram_d_io[4]
+set_location_assignment PIN_D15 -to dram_d_io[5]
+set_location_assignment PIN_E15 -to dram_d_io[6]
+set_location_assignment PIN_G14 -to dram_d_io[7]
+set_location_assignment PIN_G13 -to dram_d_io[8]
+set_location_assignment PIN_A17 -to dram_d_io[9]
+set_location_assignment PIN_B17 -to dram_d_io[10]
+set_location_assignment PIN_A16 -to dram_d_io[11]
+set_location_assignment PIN_B16 -to dram_d_io[12]
+set_location_assignment PIN_C15 -to dram_d_io[13]
+set_location_assignment PIN_E14 -to dram_d_io[14]
+set_location_assignment PIN_F13 -to dram_d_io[15]
+set_location_assignment PIN_B15 -to dram_cke_o
+set_location_assignment PIN_C13 -to dram_ldqm_o
+set_location_assignment PIN_D13 -to dram_udqm_o
+set_location_assignment PIN_E13 -to dram_we_n_o
+set_location_assignment PIN_A14 -to dram_cas_n_o
+set_location_assignment PIN_B14 -to dram_ras_n_o
+set_location_assignment PIN_A13 -to dram_cs_n_o
+set_location_assignment PIN_B13 -to dram_ba0_n_o
+set_location_assignment PIN_E12 -to dram_ba1_n_o
+set_location_assignment PIN_F11 -to dram_a_o[12]
+
+# FPGA bank 8
+# -----------
+#set_location_assignment PIN_D10 -to sdfe_dout_0_i
+#set_location_assignment PIN_E10 -to sdfe_din_0_o
+#set_location_assignment PIN_A10 -to sdfe_aux_0_0_o
+#set_location_assignment PIN_B10 -to sdfe_aux_0_1_o
+#set_location_assignment PIN_A9 -to sdfe_aux_0_2_o
+#set_location_assignment PIN_B9 -to sdfe_aux_0_3_i
+#set_location_assignment PIN_C10 -to sdfe_aux_0_4_i
+#set_location_assignment PIN_G11 -to sdfe_aux_0_5_i
+#set_location_assignment PIN_A8 -to sdfe_refclk_0_i
+set_location_assignment PIN_B8 -to reserve8_i
+#set_location_assignment PIN_B7 -to sdfe_dout_3_i
+#set_location_assignment PIN_A6 -to sdfe_din_3_o
+#set_location_assignment PIN_B6 -to sdfe_aux_3_0_o
+#set_location_assignment PIN_E9 -to sdfe_aux_3_1_o
+#set_location_assignment PIN_C8 -to sdfe_aux_3_2_o
+#set_location_assignment PIN_C7 -to sdfe_aux_3_3_i
+#set_location_assignment PIN_H11 -to sdfe_aux_3_4_i
+#set_location_assignment PIN_H10 -to sdfe_aux_3_5_i
+#set_location_assignment PIN_A5 -to sdfe_refclk_3_i
+set_location_assignment PIN_B5 -to gen_led_r_o[1]
+set_location_assignment PIN_G10 -to gen_led_g_o[1]
+#set_location_assignment PIN_F10 -to sdfe_scdi_o
+#set_location_assignment PIN_C6 -to sdfe_scdo_i
+#set_location_assignment PIN_D7 -to sdfe_scck_o
+#set_location_assignment PIN_A4 -to rst_sdfe_n_o
+#set_location_assignment PIN_B4 -to mprdy_n_io
+#set_location_assignment PIN_F8 -to mpcs_n_o
+#set_location_assignment PIN_G8 -to mpwr_n_o
+#set_location_assignment PIN_A3 -to mprd_n_o
+#set_location_assignment PIN_B3 -to mpint_n_i
+#set_location_assignment PIN_D6 -to mpclk_o
+#set_location_assignment PIN_E7 -to isdn_cs_n_o
+#set_location_assignment PIN_C3 -to mpad_o[0]
+#set_location_assignment PIN_C4 -to mpad_o[1]
+#set_location_assignment PIN_F7 -to mpad_o[2]
+#set_location_assignment PIN_G7 -to mpad_o[3]
+#set_location_assignment PIN_F9 -to mpad_o[4]
+#set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+
+set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_reset_n_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reserve8_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_r_o[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_g_o[1]
+
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name QUARTUS_PTF_FILE dionysos_nios2mmu.ptf
+set_global_assignment -name SOPC_FILE dionysos_nios2mmu.sopc
+set_global_assignment -name SOURCE_FILE dionysos_nios2mmu.sopcinfo
+set_global_assignment -name VHDL_FILE dionysos_nios2mmu.vhd
+set_global_assignment -name VHDL_FILE ../lib/misc/components/reset_sync.vhd
+set_global_assignment -name VHDL_FILE ../dionysos_top.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/quartus/dionysos_nios2mmu.sdc b/quartus/dionysos_nios2mmu.sdc
new file mode 100644
index 0000000..a4948ef
--- /dev/null
+++ b/quartus/dionysos_nios2mmu.sdc
@@ -0,0 +1,202 @@
+##
+## DEVICE "EP3C40F484C6"
+##
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {clock_50} -period 20.000 [get_ports {clock_50_i}]
+
+# Write and Read Clock for the EPCS16N-98364 device
+#----------------------
+create_clock -name epcs_wd_clk -period 25MHz [get_ports config_dclk_o]
+create_clock -name epcs_rd_clk -period 20MHz -add [get_ports config_dclk_o]
+
+# JTAG: constrain the TCK port [Quartus II TimeQuest Timing Analyzer Cookbook]
+#-----------------------------------------------------------------------------
+#create_clock -name tck -period 10MHz [get_ports altera_reserved_tck]
+
+#**************************************************************
+# Create Generated Clock (Used for Clock relations (PLL))
+#**************************************************************
+
+# connected via PLL (Normal Mode, -3ns phase shift
+create_generated_clock -name pll_1_clk_3 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \
+ -phase -54.000 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[3]}]
+
+create_generated_clock -name clock_dram -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[3]}] \
+ [get_ports {dram_clk_o}]
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+# EPCS16N-98364 (EPCS): cut all paths between the write and read clock (just one of both is active at any time)
+set_clock_groups -asynchronous -group [get_clocks epcs_wd_clk] -group [get_clocks epcs_rd_clk] -group [get_clocks {pll_1_clk_0}]
+
+# JTAG: cut all paths to and from tck
+#set_clock_groups -asynchronous -group [get_clocks tck]
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+set_clock_uncertainty -from { pll_1_clk_0 } -to { pll_1_clk_0 } 0.2
+set_clock_uncertainty -from { pll_1_clk_0 } -to { pll_1_clk_1 } 0.2
+set_clock_uncertainty -from { pll_1_clk_0 } -to { clock_dram } 0.2
+
+set_clock_uncertainty -from { pll_1_clk_1 } -to { pll_1_clk_1 } 0.2
+set_clock_uncertainty -from { pll_1_clk_1 } -to { pll_1_clk_0 } 0.2
+
+set_clock_uncertainty -from { pll_1_clk_2 } -to { pll_1_clk_2 } 0.2
+set_clock_uncertainty -from { pll_1_clk_2 } -to { pll_1_clk_0 } 0.2
+
+set_clock_uncertainty -from { et_phy_clk } -to { pll_1_clk_0 } 0.2
+
+set_clock_uncertainty -from { clock_dram } -to { clock_dram } 0.2
+set_clock_uncertainty -from { clock_dram } -to { pll_1_clk_0 } 0.2
+
+set_clock_uncertainty -from { clock_ssram } -to { pll_1_clk_0 } 0.2
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+# SDRAM Timing Constraints IS42S16800D-7TL
+#-------------------
+# CAS Latency (Latency = 3), Access Time From CLK: t_AC = 6.5 ns
+set_input_delay -max -clock [get_clocks {clock_dram}] 6.500 [get_ports {dram_d_io[*]}]
+# CAS Latency (Latency = 3), Output Data Hold Time: t_OH = 2.7 ns
+set_input_delay -min -clock [get_clocks {clock_dram}] 2.700 [get_ports {dram_d_io[*]}]
+
+# EPCS16N-98364 (EPCS)
+#-------------------
+# Read Operation Timing, Clock Falling Edge to Data: t_nCLK2D = 15 ns (FROM FALLING CLOCK EDGE)
+set_input_delay -max -clock_fall -clock epcs_rd_clk 15.000 [get_ports {config_data0_i}]
+# Read Operation Timing, Output Hold time is not known, therfore we chosse 0 ns (FROM FALLING CLOCK EDGE)
+set_input_delay -min -clock_fall -clock epcs_rd_clk 0.000 [get_ports {config_data0_i}]
+
+# JTAG: constrain the TDI and TMS port [Quartus II TimeQuest Timing Analyzer Cookbook]
+#-------------------------------------------------------------------------------------
+#set_input_delay -clock tck 20 \
+# [get_ports altera_reserved_tdi]
+#set_input_delay -clock tck 20 \
+# [get_ports altera_reserved_tms]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+# SDRAM Timing Constraints IS42S16800D-7TL
+#-------------------
+# Address/Input Data/CKE/COMMAND Setup Time: t_AS, t_DS, t_CKS, t_CS = 1.5 ns
+set_output_delay -max -clock [get_clocks {clock_dram}] 1.500 [get_ports {dram_a_o[*] dram_d_io[*] \
+ dram_cke_o dram_ba?_n_o dram_cs_n_o \
+ dram_ras_n_o dram_cas_n_o dram_we_n_o dram_ldqm_o dram_udqm_o}]
+# Address/Input Data/CKE/COMMAND Hold Time: t_AH, t_DH, t_CKH, t_CH = 0.8 ns
+set_output_delay -min -clock [get_clocks {clock_dram}] -0.800 [get_ports {dram_a_o[*] dram_d_io[*] \
+ dram_cke_o dram_ba?_n_o dram_cs_n_o \
+ dram_ras_n_o dram_cas_n_o dram_we_n_o dram_ldqm_o dram_udqm_o}]
+
+# EPCS16N-98364 (EPCS)
+#-------------------
+# Write Operation Timing, Data In Setup time: t_DSU = 5 ns
+set_output_delay -max -clock epcs_wd_clk 5.000 [get_ports config_asd0_o]
+# Write Operation Timing, Data In Hold time: t_DH = 5 ns
+set_output_delay -min -clock epcs_wd_clk -5.000 [get_ports config_asd0_o]
+
+# Write Operation Timing, Chip select Setup time: t_NCSSU = 10 ns
+set_output_delay -max -clock epcs_wd_clk 10.000 [get_ports config_ce_n_o]
+
+# Write Operation Timing, Chip select Hold time: t_NCSH = 10 ns
+set_output_delay -min -clock epcs_wd_clk -10.000 [get_ports config_ce_n_o]
+
+# JTAG: constrain the TDO port [Quartus II TimeQuest Timing Analyzer Cookbook]
+#-----------------------------------------------------------------------------
+#set_output_delay -clock tck 20 \
+# [get_ports altera_reserved_tdo]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+# Main input reset
+#-------------------
+set_false_path -from [get_ports {fpga_reset_n_i}]
+
+# NIOS CPU
+#-------------------
+# Nios uart signals (RS232)
+set_false_path -from [get_ports {nios_uart_rxd_i}]
+set_false_path -to [get_ports {nios_uart_txd_o}]
+
+# GP-LEDs
+#-------------------
+set_false_path -to [get_ports {gp_led_o[*] gen_led_g_o[*] gen_led_r_o[*]}]
+
+# Switch Input
+#-------------------
+set_false_path -from [get_ports {switch_i[*]}]
+
+# Reserve Pins
+#-------------------
+set_false_path -from [get_ports {reserve?_i}]
+
+# Parallel Flash (S29AL032D 70TF100)
+# timing is to do in SOPC System
+#-------------------
+set_false_path -from [get_ports {flash_d_io[*]}]
+set_false_path -to [get_ports {flash_d_io[*] flash_a_o[*] flash_we_n_o flash_reset_n_o flash_oe_n_o flash_ce_n_o fash_acc_o}]
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+# compensate the negative phase shift of the output SDRAM clock for hold check
+# clock_50 ___|----|____|----|
+# clock_dram_pll __|----|____|----|
+# Compensate setup path from clock_50 to clock_dram_pll
+set_multicycle_path -from [get_clocks pll_1_clk_0] \
+ -to [get_clocks clock_dram] \
+ -setup -end 1
+
+# Compensate hold path from clock_dram_pll to clock_50 (default sdc configuration)
+set_multicycle_path -from [get_clocks pll_1_clk_0] \
+ -to [get_clocks clock_dram] \
+ -hold -start 0
+
+# clock_dram_pll __|----|____|----|
+# clock_50 ___|----|____|----|
+# Compensate setup path from clock_dram_pll to clock_50
+set_multicycle_path -from [get_clocks clock_dram] \
+ -to [get_clocks pll_1_clk_0] \
+ -setup -start 2
+
+# Hold is already correct and has not to be defined
+
+#set_multicycle_path -from [get_clocks {clock_50}] \
+# -to [get_fanouts [get_registers {clk_50_en}]] \
+# -hold -end 1
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
diff --git a/quartus/dionysos_nios2mmu.sopc b/quartus/dionysos_nios2mmu.sopc
new file mode 100644
index 0000000..6bbc587
--- /dev/null
+++ b/quartus/dionysos_nios2mmu.sopc
@@ -0,0 +1,566 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="dionysos_nios2mmu">
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "41951296";
+ type = "long";
+ }
+ }
+ element cfi_flash_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos-nios2mmu}";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element dionysos_nios2mmu
+ {
+ }
+ element epcs_flash_controller_0.epcs_control_port
+ {
+ datum baseAddress
+ {
+ value = "41949184";
+ type = "long";
+ }
+ }
+ element epcs_flash_controller_0
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "41947136";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "41951232";
+ type = "long";
+ }
+ }
+ element uart_0.s1
+ {
+ datum baseAddress
+ {
+ value = "41951264";
+ type = "long";
+ }
+ }
+ element sdram_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "16777216";
+ type = "long";
+ }
+ }
+ element cfi_flash_0.s1
+ {
+ datum baseAddress
+ {
+ value = "37748736";
+ type = "long";
+ }
+ }
+ element sdram_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos-nios2mmu}";
+ type = "String";
+ }
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element tri_state_bridge_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element uart_0
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="deviceFamily" value="CYCLONEIII" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="hardcopyCompatible" value="false" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="projectName">dionysos-nios2mmu.qpf</parameter>
+ <parameter name="systemHash" value="-19653124377" />
+ <parameter name="timeStamp" value="1269273057814" />
+ <module name="clk_0" kind="clock_source" version="9.1" enabled="1">
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ </module>
+ <module name="cpu_0" kind="altera_nios2" version="9.1" enabled="1">
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_perfCounterWidth" value="_32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtPtrSz" value="_8" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="resetSlave" value="cfi_flash_0.s1" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_minInstRegionSize" value="_12" />
+ <parameter name="mpu_minDataRegionSize" value="_12" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_uitlbNumEntries" value="_4" />
+ <parameter name="mmu_udtlbNumEntries" value="_6" />
+ <parameter name="mmu_tlbPtrSz" value="_7" />
+ <parameter name="mmu_tlbNumWays" value="_16" />
+ <parameter name="mmu_processIDNumBits" value="_8" />
+ <parameter name="mmu_enabled" value="true" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_TLBMissExcSlave" value="onchip_memory2_0.s1" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="impl" value="Fast" />
+ <parameter name="icache_size" value="_4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="_1" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="exceptionSlave" value="sdram_0.s1" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="_2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_numTCDM" value="_1" />
+ <parameter name="dcache_lineSize" value="_32" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="breakOffset" value="32" />
+ </module>
+ <module
+ name="sdram_0"
+ kind="altera_avalon_new_sdram_controller"
+ version="9.1"
+ enabled="1">
+ <parameter name="TAC" value="5.5" />
+ <parameter name="TMRD" value="3" />
+ <parameter name="TRCD" value="20.0" />
+ <parameter name="TRFC" value="70.0" />
+ <parameter name="TRP" value="20.0" />
+ <parameter name="TWR" value="14.0" />
+ <parameter name="casLatency" value="3" />
+ <parameter name="columnWidth" value="9" />
+ <parameter name="dataWidth" value="16" />
+ <parameter name="generateSimulationModel" value="true" />
+ <parameter name="initNOPDelay" value="0.0" />
+ <parameter name="initRefreshCommands" value="2" />
+ <parameter name="masteredTristateBridgeSlave" value="" />
+ <parameter name="model" value="custom" />
+ <parameter name="numberOfBanks" value="4" />
+ <parameter name="numberOfChipSelects" value="1" />
+ <parameter name="pinsSharedViaTriState" value="false" />
+ <parameter name="powerUpDelay" value="100.0" />
+ <parameter name="refreshPeriod" value="15.625" />
+ <parameter name="registerDataIn" value="true" />
+ <parameter name="rowWidth" value="12" />
+ </module>
+ <module
+ name="tri_state_bridge_0"
+ kind="altera_avalon_tri_state_bridge"
+ version="9.1"
+ enabled="1">
+ <parameter name="registerIncomingSignals" value="true" />
+ </module>
+ <module
+ name="cfi_flash_0"
+ kind="altera_avalon_cfi_flash"
+ version="9.1"
+ enabled="1">
+ <parameter name="addressWidth" value="22" />
+ <parameter name="corePreset" value="CUSTOM" />
+ <parameter name="dataWidth" value="8" />
+ <parameter name="holdTime" value="40" />
+ <parameter name="setupTime" value="40" />
+ <parameter name="sharedPorts">s1/address,s1/data,s1/read_n</parameter>
+ <parameter name="timingUnits" value="NS" />
+ <parameter name="waitTime" value="160" />
+ </module>
+ <module
+ name="epcs_flash_controller_0"
+ kind="altera_avalon_epcs_flash_controller"
+ version="9.1"
+ enabled="1">
+ <parameter name="autoSelectASMIAtom" value="true" />
+ <parameter name="useASMIAtom" value="false" />
+ </module>
+ <module name="timer_0" kind="altera_avalon_timer" version="9.1" enabled="1">
+ <parameter name="alwaysRun" value="false" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="false" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="true" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset" value="CUSTOM" />
+ </module>
+ <module name="uart_0" kind="altera_avalon_uart" version="9.1" enabled="1">
+ <parameter name="baud" value="115200" />
+ <parameter name="dataBits" value="8" />
+ <parameter name="fixedBaud" value="true" />
+ <parameter name="parity" value="NONE" />
+ <parameter name="simCharStream" value="" />
+ <parameter name="simInteractiveInputEnable" value="false" />
+ <parameter name="simInteractiveOutputEnable" value="false" />
+ <parameter name="simTrueBaud" value="false" />
+ <parameter name="stopBits" value="1" />
+ <parameter name="syncRegDepth" value="2" />
+ <parameter name="useCtsRts" value="false" />
+ <parameter name="useEopRegister" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ </module>
+ <module
+ name="jtag_uart_0"
+ kind="altera_avalon_jtag_uart"
+ version="9.1"
+ enabled="1">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream" value="" />
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module
+ name="onchip_memory2_0"
+ kind="altera_avalon_onchip_memory2"
+ version="9.1"
+ enabled="1">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="blockType" value="AUTO" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="dualPort" value="true" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="1024" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <connection kind="clock" version="9.1" start="clk_0.clk" end="cpu_0.clk" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02801000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02801000" />
+ </connection>
+ <connection kind="clock" version="9.1" start="clk_0.clk" end="sdram_0.clk" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.instruction_master"
+ end="sdram_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01000000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="sdram_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01000000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="tri_state_bridge_0.clk" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.instruction_master"
+ end="tri_state_bridge_0.avalon_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="tri_state_bridge_0.avalon_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection kind="clock" version="9.1" start="clk_0.clk" end="cfi_flash_0.clk" />
+ <connection
+ kind="avalon_tristate"
+ version="9.1"
+ start="tri_state_bridge_0.tristate_master"
+ end="cfi_flash_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02400000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="epcs_flash_controller_0.clk" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.instruction_master"
+ end="epcs_flash_controller_0.epcs_control_port">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02801800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="epcs_flash_controller_0.epcs_control_port">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02801800" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="9.1"
+ start="cpu_0.d_irq"
+ end="epcs_flash_controller_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection kind="clock" version="9.1" start="clk_0.clk" end="timer_0.clk" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02802000" />
+ </connection>
+ <connection kind="interrupt" version="9.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="clock" version="9.1" start="clk_0.clk" end="uart_0.clk" />
+ <connection kind="avalon" version="6.1" start="cpu_0.data_master" end="uart_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02802020" />
+ </connection>
+ <connection kind="interrupt" version="9.1" start="cpu_0.d_irq" end="uart_0.irq">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection kind="clock" version="9.1" start="clk_0.clk" end="jtag_uart_0.clk" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02802040" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="9.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk2" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.tightly_coupled_instruction_master_0"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.tightly_coupled_data_master_0"
+ end="onchip_memory2_0.s2">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+</system>
diff --git a/quartus/dionysos_nios2mmu.sopcinfo b/quartus/dionysos_nios2mmu.sopcinfo
new file mode 100644
index 0000000..f3c2e42
--- /dev/null
+++ b/quartus/dionysos_nios2mmu.sopcinfo
@@ -0,0 +1,9792 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport
+ name="dionysos_nios2mmu"
+ kind="com_altera_sopcmodel_ensemble_Ensemble"
+ version="9.1">
+ <!-- Format version 9.1 222 (Future versions may contain additional information.) -->
+ <!-- 2010.03.22.16:53:15 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="deviceFamily">
+ <type>com.altera.entityinterfaces.moduleext.IDeviceFamily$EDeviceFamily</type>
+ <value>CYCLONEIII</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hardcopyCompatible">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+ <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+ <value>VHDL</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+ <type>java.lang.String</type>
+ <value>dionysos-nios2mmu.qpf</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+ <type>long</type>
+ <value>-19653124377</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+ <type>long</type>
+ <value>1269273057814</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <module name="clk_0" kind="clock_source" version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <parameter name="clockFrequency">
+ <type>long</type>
+ <value>50000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockFrequencyKnown">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="inputClockFrequency">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_source" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedDirectClock">
+ <type>java.lang.String</type>
+ <value>clk_in</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>50000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <port>
+ <name>reset_n_out</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ <port>
+ <name>clk_out</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>cpu_0</moduleName>
+ <slaveName>clk</slaveName>
+ <name>cpu_0.clk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>sdram_0</moduleName>
+ <slaveName>clk</slaveName>
+ <name>sdram_0.clk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>tri_state_bridge_0</moduleName>
+ <slaveName>clk</slaveName>
+ <name>tri_state_bridge_0.clk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>cfi_flash_0</moduleName>
+ <slaveName>clk</slaveName>
+ <name>cfi_flash_0.clk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>epcs_flash_controller_0</moduleName>
+ <slaveName>clk</slaveName>
+ <name>epcs_flash_controller_0.clk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>timer_0</moduleName>
+ <slaveName>clk</slaveName>
+ <name>timer_0.clk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>uart_0</moduleName>
+ <slaveName>clk</slaveName>
+ <name>uart_0.clk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>jtag_uart_0</moduleName>
+ <slaveName>clk</slaveName>
+ <name>jtag_uart_0.clk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>onchip_memory2_0</moduleName>
+ <slaveName>clk1</slaveName>
+ <name>onchip_memory2_0.clk1</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>onchip_memory2_0</moduleName>
+ <slaveName>clk2</slaveName>
+ <name>onchip_memory2_0.clk2</name>
+ </clockDomainMember>
+ </interface>
+ <interface name="clk_in" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>java.lang.Long</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>java.lang.Boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>in_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <port>
+ <name>in_reset_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ </module>
+ <module name="cpu_0" kind="altera_nios2" version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.configuration.cpuArchitecture</name>
+ <value>Nios II</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.HDLSimCachesCleared</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.CPU_IMPLEMENTATION</name>
+ <value>"fast"</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.BIG_ENDIAN</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.CPU_FREQ</name>
+ <value>50000000u</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.ICACHE_LINE_SIZE</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</name>
+ <value>5</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.ICACHE_SIZE</name>
+ <value>4096</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.DCACHE_LINE_SIZE</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</name>
+ <value>5</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.DCACHE_SIZE</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.INITDA_SUPPORTED</name>
+ <value></value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.FLUSHDA_SUPPORTED</name>
+ <value></value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</name>
+ <value></value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.resetSlave</name>
+ <value>cfi_flash_0.s1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.resetOffset</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.exceptionSlave</name>
+ <value>sdram_0.s1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.exceptionOffset</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.breakSlave</name>
+ <value>cpu_0.jtag_debug_module</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.breakOffset</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.MMU_PRESENT</name>
+ <value></value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.KERNEL_REGION_BASE</name>
+ <value>0xc0000000</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.IO_REGION_BASE</name>
+ <value>0xe0000000</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.KERNEL_MMU_REGION_BASE</name>
+ <value>0x80000000</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.USER_REGION_BASE</name>
+ <value>0x0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PROCESS_ID_NUM_BITS</name>
+ <value>8</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TLB_NUM_WAYS</name>
+ <value>16</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TLB_NUM_WAYS_LOG2</name>
+ <value>4</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TLB_PTR_SZ</name>
+ <value>8</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TLB_NUM_ENTRIES</name>
+ <value>256</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR</name>
+ <value>0xc0001000</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.mmu_TLBMissExcSlave</name>
+ <value>onchip_memory2_0.s1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.mmu_TLBMissExcOffset</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.EXCEPTION_ADDR</name>
+ <value>0xc1000020</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.RESET_ADDR</name>
+ <value>0xc2400000</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.BREAK_ADDR</name>
+ <value>0xc2801020</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HAS_DEBUG_STUB</name>
+ <value></value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HAS_DEBUG_CORE</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</name>
+ <value></value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION</name>
+ <value></value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO</name>
+ <value></value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.CPU_ID_SIZE</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.CPU_ID_VALUE</name>
+ <value>0x0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.INST_ADDR_WIDTH</name>
+ <value>26</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.DATA_ADDR_WIDTH</name>
+ <value>26</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS</name>
+ <value>0</value>
+ </assignment>
+ <parameter name="userDefinedSettings">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_showUnpublishedSettings">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_showInternalSettings">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_shadowRegisterSets">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_preciseSlaveAccessErrorException">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_preciseIllegalMemAccessException">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_preciseDivisionErrorException">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_performanceCounter">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_perfCounterWidth">
+ <type>com.altera.nios2.components.Nios2InternalSettings$OptPerfCounterWidth</type>
+ <value>_32</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_interruptControllerType">
+ <type>com.altera.nios2.components.Nios2InternalSettings$OptInterruptControllerType</type>
+ <value>Internal</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_illegalMemAccessDetection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_illegalInstructionsTrap">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_fullWaveformSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_extraExceptionInfo">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_exportPCB">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_debugSimGen">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_clearXBitsLDNonBypass">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_branchPredictionType">
+ <type>com.altera.nios2.components.Nios2InternalSettings$OptBranchPredictionType</type>
+ <value>Automatic</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_bit31BypassDCache">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_bigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_bhtPtrSz">
+ <type>com.altera.nios2.components.Nios2InternalSettings$OptBhtPtrSz</type>
+ <value>_8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_bhtIndexPcOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_avalonDebugPortPresent">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_alwaysEncrypt">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_allowFullAddressRange">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_activateTrace">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_activateTestEndChecker">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_activateMonitors">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_activateModelChecker">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_HDLSimCachesCleared">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setting_HBreakTest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="resetSlave">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>cfi_flash_0.s1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="resetOffset">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="muldiv_multiplierType">
+ <type>com.altera.nios2.components.Nios2MultiplierDivider$OptMultiplier</type>
+ <value>EmbeddedMulFast</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="muldiv_divider">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mpu_useLimit">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mpu_numOfInstRegion">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mpu_numOfDataRegion">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mpu_minInstRegionSize">
+ <type>com.altera.nios2.components.Nios2MPU$OptRegionSize</type>
+ <value>_12</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mpu_minDataRegionSize">
+ <type>com.altera.nios2.components.Nios2MPU$OptRegionSize</type>
+ <value>_12</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mpu_enabled">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_uitlbNumEntries">
+ <type>com.altera.nios2.components.Nios2MMU$OptTlbNumEntries</type>
+ <value>_4</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_udtlbNumEntries">
+ <type>com.altera.nios2.components.Nios2MMU$OptTlbNumEntries</type>
+ <value>_6</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_tlbPtrSz">
+ <type>com.altera.nios2.components.Nios2MMU$OptTlbPtrSz</type>
+ <value>_7</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_tlbNumWays">
+ <type>com.altera.nios2.components.Nios2MMU$OptTlbNumWays</type>
+ <value>_16</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_processIDNumBits">
+ <type>com.altera.nios2.components.Nios2MMU$OptProcessIDNumBits</type>
+ <value>_8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_enabled">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_autoAssignTlbPtrSz">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_TLBMissExcSlave">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>onchip_memory2_0.s1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mmu_TLBMissExcOffset">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="manuallyAssignCpuID">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="impl">
+ <type>com.altera.nios2.components.INios2Component$Impl</type>
+ <value>Fast</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="icache_size">
+ <type>com.altera.nios2.components.Nios2AbstractCache$OptBytes</type>
+ <value>_4096</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="icache_ramBlockType">
+ <type>com.altera.nios2.components.Nios2AbstractCache$OptRamBlockType</type>
+ <value>Automatic</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="icache_numTCIM">
+ <type>com.altera.nios2.components.Nios2AbstractCache$OptNumTCM</type>
+ <value>_1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="icache_burstType">
+ <type>com.altera.nios2.components.Nios2ICache$OptBurstType</type>
+ <value>None</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="exceptionSlave">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>sdram_0.s1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="exceptionOffset">
+ <type>long</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="debug_triggerArming">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="debug_level">
+ <type>com.altera.nios2.components.Nios2Debug$OptLevel</type>
+ <value>Level1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="debug_jtagInstanceID">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="debug_embeddedPLL">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="debug_debugReqSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="debug_assignJtagInstanceID">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="debug_OCIOnchipTrace">
+ <type>com.altera.nios2.components.Nios2Debug$OptOCIOnchipTrace</type>
+ <value>_128</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dcache_size">
+ <type>com.altera.nios2.components.Nios2AbstractCache$OptBytes</type>
+ <value>_2048</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dcache_ramBlockType">
+ <type>com.altera.nios2.components.Nios2AbstractCache$OptRamBlockType</type>
+ <value>Automatic</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dcache_omitDataMaster">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dcache_numTCDM">
+ <type>com.altera.nios2.components.Nios2AbstractCache$OptNumTCM</type>
+ <value>_1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dcache_lineSize">
+ <type>com.altera.nios2.components.Nios2DCache$OptLineSize</type>
+ <value>_32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dcache_bursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="cpuReset">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="cpuID">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockFrequency">
+ <type>long</type>
+ <value>50000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="breakSlave">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>cpu_0.jtag_debug_module</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="breakOffset">
+ <type>long</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>java.lang.Long</type>
+ <value>50000000</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>java.lang.Boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <port>
+ <name>reset_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ <interface name="instruction_master" kind="avalon_master" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="adaptsTo">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>SYMBOLS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dBSBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="doStreamReads">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="doStreamWrites">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isAsynchronous">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isReadable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isWriteable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxAddressWidth">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>true</isStart>
+ <port>
+ <name>i_address</name>
+ <direction>Output</direction>
+ <width>26</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>i_read</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>read</role>
+ </port>
+ <port>
+ <name>i_readdata</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>i_readdatavalid</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>readdatavalid</role>
+ </port>
+ <port>
+ <name>i_waitrequest</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>waitrequest</role>
+ </port>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>cpu_0</moduleName>
+ <slaveName>jtag_debug_module</slaveName>
+ <name>cpu_0.jtag_debug_module</name>
+ <baseAddress>41947136</baseAddress>
+ <span>2048</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>sdram_0</moduleName>
+ <slaveName>s1</slaveName>
+ <name>sdram_0.s1</name>
+ <baseAddress>16777216</baseAddress>
+ <span>16777216</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>cfi_flash_0</moduleName>
+ <slaveName>s1</slaveName>
+ <name>cfi_flash_0.s1</name>
+ <baseAddress>37748736</baseAddress>
+ <span>4194304</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>epcs_flash_controller_0</moduleName>
+ <slaveName>epcs_control_port</slaveName>
+ <name>epcs_flash_controller_0.epcs_control_port</name>
+ <baseAddress>41949184</baseAddress>
+ <span>2048</span>
+ </memoryBlock>
+ </interface>
+ <interface
+ name="tightly_coupled_instruction_master_0"
+ kind="avalon_master"
+ version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="adaptsTo">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>SYMBOLS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dBSBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="doStreamReads">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="doStreamWrites">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isAsynchronous">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isReadable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isWriteable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxAddressWidth">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>true</isStart>
+ <port>
+ <name>icm0_address</name>
+ <direction>Output</direction>
+ <width>26</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>icm0_read</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>read</role>
+ </port>
+ <port>
+ <name>icm0_readdata</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>icm0_readdatavalid</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>readdatavalid</role>
+ </port>
+ <port>
+ <name>icm0_waitrequest</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>waitrequest</role>
+ </port>
+ <port>
+ <name>icm0_clken</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>clken</role>
+ </port>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>onchip_memory2_0</moduleName>
+ <slaveName>s1</slaveName>
+ <name>onchip_memory2_0.s1</name>
+ <baseAddress>4096</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
+ </interface>
+ <interface name="data_master" kind="avalon_master" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="adaptsTo">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>SYMBOLS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dBSBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="doStreamReads">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="doStreamWrites">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isAsynchronous">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isReadable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isWriteable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxAddressWidth">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>true</isStart>
+ <port>
+ <name>d_address</name>
+ <direction>Output</direction>
+ <width>26</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>d_byteenable</name>
+ <direction>Output</direction>
+ <width>4</width>
+ <role>byteenable</role>
+ </port>
+ <port>
+ <name>d_read</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>read</role>
+ </port>
+ <port>
+ <name>d_readdata</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>d_readdatavalid</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>readdatavalid</role>
+ </port>
+ <port>
+ <name>d_waitrequest</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>waitrequest</role>
+ </port>
+ <port>
+ <name>d_write</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>write</role>
+ </port>
+ <port>
+ <name>d_writedata</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_debugaccess_to_roms</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>debugaccess</role>
+ </port>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>cpu_0</moduleName>
+ <slaveName>jtag_debug_module</slaveName>
+ <name>cpu_0.jtag_debug_module</name>
+ <baseAddress>41947136</baseAddress>
+ <span>2048</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>sdram_0</moduleName>
+ <slaveName>s1</slaveName>
+ <name>sdram_0.s1</name>
+ <baseAddress>16777216</baseAddress>
+ <span>16777216</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>cfi_flash_0</moduleName>
+ <slaveName>s1</slaveName>
+ <name>cfi_flash_0.s1</name>
+ <baseAddress>37748736</baseAddress>
+ <span>4194304</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>epcs_flash_controller_0</moduleName>
+ <slaveName>epcs_control_port</slaveName>
+ <name>epcs_flash_controller_0.epcs_control_port</name>
+ <baseAddress>41949184</baseAddress>
+ <span>2048</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>timer_0</moduleName>
+ <slaveName>s1</slaveName>
+ <name>timer_0.s1</name>
+ <baseAddress>41951232</baseAddress>
+ <span>32</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>uart_0</moduleName>
+ <slaveName>s1</slaveName>
+ <name>uart_0.s1</name>
+ <baseAddress>41951264</baseAddress>
+ <span>32</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>jtag_uart_0</moduleName>
+ <slaveName>avalon_jtag_slave</slaveName>
+ <name>jtag_uart_0.avalon_jtag_slave</name>
+ <baseAddress>41951296</baseAddress>
+ <span>8</span>
+ </memoryBlock>
+ </interface>
+ <interface name="d_irq" kind="interrupt_receiver" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedAddressablePoint">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>cpu_0.data_master</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="irqScheme">
+ <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+ <value>INDIVIDUAL_REQUESTS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>interrupt</type>
+ <isStart>true</isStart>
+ <port>
+ <name>d_irq</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>irq</role>
+ </port>
+ <interrupt>
+ <isBridge>false</isBridge>
+ <moduleName>epcs_flash_controller_0</moduleName>
+ <slaveName>irq</slaveName>
+ <name>epcs_flash_controller_0.irq</name>
+ <interruptNumber>1</interruptNumber>
+ </interrupt>
+ <interrupt>
+ <isBridge>false</isBridge>
+ <moduleName>timer_0</moduleName>
+ <slaveName>irq</slaveName>
+ <name>timer_0.irq</name>
+ <interruptNumber>0</interruptNumber>
+ </interrupt>
+ <interrupt>
+ <isBridge>false</isBridge>
+ <moduleName>uart_0</moduleName>
+ <slaveName>irq</slaveName>
+ <name>uart_0.irq</name>
+ <interruptNumber>2</interruptNumber>
+ </interrupt>
+ <interrupt>
+ <isBridge>false</isBridge>
+ <moduleName>jtag_uart_0</moduleName>
+ <slaveName>irq</slaveName>
+ <name>jtag_uart_0.irq</name>
+ <interruptNumber>3</interruptNumber>
+ </interrupt>
+ </interface>
+ <interface
+ name="tightly_coupled_data_master_0"
+ kind="avalon_master"
+ version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="adaptsTo">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>SYMBOLS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dBSBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="doStreamReads">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="doStreamWrites">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isAsynchronous">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isReadable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isWriteable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxAddressWidth">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>true</isStart>
+ <port>
+ <name>dcm0_address</name>
+ <direction>Output</direction>
+ <width>26</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>dcm0_byteenable</name>
+ <direction>Output</direction>
+ <width>4</width>
+ <role>byteenable</role>
+ </port>
+ <port>
+ <name>dcm0_clken</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>clken</role>
+ </port>
+ <port>
+ <name>dcm0_read</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>read</role>
+ </port>
+ <port>
+ <name>dcm0_readdata</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>dcm0_readdatavalid</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>readdatavalid</role>
+ </port>
+ <port>
+ <name>dcm0_waitrequest</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>waitrequest</role>
+ </port>
+ <port>
+ <name>dcm0_write</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>write</role>
+ </port>
+ <port>
+ <name>dcm0_writedata</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>onchip_memory2_0</moduleName>
+ <slaveName>s2</slaveName>
+ <name>onchip_memory2_0.s2</name>
+ <baseAddress>0</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
+ </interface>
+ <interface name="jtag_debug_module" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.hideDevice</name>
+ <value>1</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>2048</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>jtag_debug_module_address</name>
+ <direction>Input</direction>
+ <width>9</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_begintransfer</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>begintransfer</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_byteenable</name>
+ <direction>Input</direction>
+ <width>4</width>
+ <role>byteenable</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_debugaccess</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>debugaccess</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_readdata</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_resetrequest</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>resetrequest</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_select</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_write</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write</role>
+ </port>
+ <port>
+ <name>jtag_debug_module_writedata</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ </interface>
+ <interface
+ name="custom_instruction_master"
+ kind="nios_custom_instruction_master"
+ version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="CIName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressWidth">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enabled">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxAddressWidth">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="opcodeExtension">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>nios_custom_instruction</type>
+ <isStart>true</isStart>
+ <port>
+ <name>dataa</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>dataa</role>
+ </port>
+ <port>
+ <name>datab</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>datab</role>
+ </port>
+ <port>
+ <name>result</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>result</role>
+ </port>
+ <port>
+ <name>clk_en</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>clk_en</role>
+ </port>
+ <port>
+ <name>reset</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>reset</role>
+ </port>
+ <port>
+ <name>start</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>start</role>
+ </port>
+ <port>
+ <name>done</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>done</role>
+ </port>
+ <port>
+ <name>n</name>
+ <direction>Output</direction>
+ <width>8</width>
+ <role>n</role>
+ </port>
+ <port>
+ <name>a</name>
+ <direction>Output</direction>
+ <width>5</width>
+ <role>a</role>
+ </port>
+ <port>
+ <name>b</name>
+ <direction>Output</direction>
+ <width>5</width>
+ <role>b</role>
+ </port>
+ <port>
+ <name>c</name>
+ <direction>Output</direction>
+ <width>5</width>
+ <role>c</role>
+ </port>
+ <port>
+ <name>readra</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>readra</role>
+ </port>
+ <port>
+ <name>readrb</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>readrb</role>
+ </port>
+ <port>
+ <name>writerc</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>writerc</role>
+ </port>
+ </interface>
+ </module>
+ <module
+ name="sdram_0"
+ kind="altera_avalon_new_sdram_controller"
+ version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.REGISTER_DATA_IN</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SIM_MODEL_BASE</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SDRAM_DATA_WIDTH</name>
+ <value>16</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SDRAM_ADDR_WIDTH</name>
+ <value>23</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SDRAM_ROW_WIDTH</name>
+ <value>12</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SDRAM_COL_WIDTH</name>
+ <value>9</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SDRAM_NUM_CHIPSELECTS</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SDRAM_NUM_BANKS</name>
+ <value>4</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.REFRESH_PERIOD</name>
+ <value>15.625</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.POWERUP_DELAY</name>
+ <value>100.0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.CAS_LATENCY</name>
+ <value>3</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.T_RFC</name>
+ <value>70.0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.T_RP</name>
+ <value>20.0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.T_MRD</name>
+ <value>3</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.T_RCD</name>
+ <value>20.0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.T_AC</name>
+ <value>5.5</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.T_WR</name>
+ <value>14.0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.INIT_REFRESH_COMMANDS</name>
+ <value>2</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.INIT_NOP_DELAY</name>
+ <value>0.0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SHARED_DATA</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.STARVATION_INDICATOR</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TRISTATE_BRIDGE_SLAVE</name>
+ <value>""</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.IS_INITIALIZED</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SDRAM_BANK_WIDTH</name>
+ <value>2</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.CONTENTS_INFO</name>
+ <value>""</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+ <value>16</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+ <value>SIM_DIR</value>
+ </assignment>
+ <parameter name="TAC">
+ <type>double</type>
+ <value>5.5</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="TMRD">
+ <type>long</type>
+ <value>3</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="TRCD">
+ <type>double</type>
+ <value>20.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="TRFC">
+ <type>double</type>
+ <value>70.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="TRP">
+ <type>double</type>
+ <value>20.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="TWR">
+ <type>double</type>
+ <value>14.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="casLatency">
+ <type>int</type>
+ <value>3</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>50000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="columnWidth">
+ <type>int</type>
+ <value>9</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dataWidth">
+ <type>int</type>
+ <value>16</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateSimulationModel">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="initNOPDelay">
+ <type>double</type>
+ <value>0.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="initRefreshCommands">
+ <type>int</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="masteredTristateBridgeSlave">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="model">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonSDRAMController.ModelMangler$PresetModels</type>
+ <value>custom</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="numberOfBanks">
+ <type>int</type>
+ <value>4</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="numberOfChipSelects">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="pinsSharedViaTriState">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="powerUpDelay">
+ <type>double</type>
+ <value>100.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="refreshPeriod">
+ <type>double</type>
+ <value>15.625</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerDataIn">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rowWidth">
+ <type>int</type>
+ <value>12</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="size">
+ <type>long</type>
+ <value>16777216</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>java.lang.Long</type>
+ <value>50000000</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>java.lang.Boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <port>
+ <name>reset_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ <interface name="s1" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>1</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>16777216</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>7</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>az_addr</name>
+ <direction>Input</direction>
+ <width>23</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>az_be_n</name>
+ <direction>Input</direction>
+ <width>2</width>
+ <role>byteenable_n</role>
+ </port>
+ <port>
+ <name>az_cs</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect</role>
+ </port>
+ <port>
+ <name>az_data</name>
+ <direction>Input</direction>
+ <width>16</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>az_rd_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>read_n</role>
+ </port>
+ <port>
+ <name>az_wr_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write_n</role>
+ </port>
+ <port>
+ <name>za_data</name>
+ <direction>Output</direction>
+ <width>16</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>za_valid</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>readdatavalid</role>
+ </port>
+ <port>
+ <name>za_waitrequest</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>waitrequest</role>
+ </port>
+ </interface>
+ <interface name="wire" kind="conduit" version="7.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>zs_addr</name>
+ <direction>Output</direction>
+ <width>12</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>zs_ba</name>
+ <direction>Output</direction>
+ <width>2</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>zs_cas_n</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>zs_cke</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>zs_cs_n</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>zs_dq</name>
+ <direction>Output</direction>
+ <width>16</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>zs_dqm</name>
+ <direction>Output</direction>
+ <width>2</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>zs_ras_n</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>zs_we_n</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ </interface>
+ </module>
+ <module
+ name="tri_state_bridge_0"
+ kind="altera_avalon_tri_state_bridge"
+ version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ </interface>
+ <interface name="avalon_slave" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isFlash</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isNonVolatileStorage</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isPrintableDevice</name>
+ <value>0</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>tri_state_bridge_0.tristate_master</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ </interface>
+ <interface name="tristate_master" kind="avalon_tristate_master" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="adaptsTo">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dBSBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isAsynchronous">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isReadable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isWriteable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxAddressWidth">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon_tristate</type>
+ <isStart>true</isStart>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>cfi_flash_0</moduleName>
+ <slaveName>s1</slaveName>
+ <name>cfi_flash_0.s1</name>
+ <baseAddress>37748736</baseAddress>
+ <span>4194304</span>
+ </memoryBlock>
+ </interface>
+ </module>
+ <module name="cfi_flash_0" kind="altera_avalon_cfi_flash" version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.SETUP_VALUE</name>
+ <value>40</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.WAIT_VALUE</name>
+ <value>160</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.HOLD_VALUE</name>
+ <value>40</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TIMING_UNITS</name>
+ <value>"ns"</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SIZE</name>
+ <value>4194304u</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+ <value>8</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.IS_FLASH</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.GENERATE_FLASH</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+ <value>SIM_DIR</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.FLASH_INSTALL_DIR</name>
+ <value>APP_DIR</value>
+ </assignment>
+ <parameter name="actualHoldTime">
+ <type>double</type>
+ <value>40.0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="actualSetupTime">
+ <type>double</type>
+ <value>40.0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="actualWaitTime">
+ <type>double</type>
+ <value>160.0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressWidth">
+ <type>int</type>
+ <value>22</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>50000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="corePreset">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonCommonFlashInterface.FlashCorePresets</type>
+ <value>CUSTOM</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dataWidth">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>40</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>40</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="sharedPorts">
+ <type>[Ljava.lang.String;</type>
+ <value>s1/address,s1/data,s1/read_n</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonCommonFlashInterface.FlashTimingUnits</type>
+ <value>NS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="waitTime">
+ <type>int</type>
+ <value>160</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>java.lang.Long</type>
+ <value>50000000</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>java.lang.Boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ </interface>
+ <interface name="s1" kind="avalon_tristate_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isNonVolatileStorage</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isFlash</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>1</value>
+ </assignment>
+ <parameter name="activeCSThroughReadLatency">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>4194304</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>40</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>160</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>160</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>40</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Nanoseconds</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>160</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>160</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon_tristate</type>
+ <isStart>false</isStart>
+ <port>
+ <name>data</name>
+ <direction>Bidir</direction>
+ <width>8</width>
+ <role>data</role>
+ </port>
+ <port>
+ <name>address</name>
+ <direction>Input</direction>
+ <width>22</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>read_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>read_n</role>
+ </port>
+ <port>
+ <name>write_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write_n</role>
+ </port>
+ <port>
+ <name>select_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect_n</role>
+ </port>
+ </interface>
+ </module>
+ <module
+ name="epcs_flash_controller_0"
+ kind="altera_avalon_epcs_flash_controller"
+ version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.REGISTER_OFFSET</name>
+ <value>1024</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
+ <value>epcs_flash_controller_0_boot_rom</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.IS_EPCS</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.IS_FLASH</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.GENERATE_FLASH</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+ <value>SIM_DIR</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+ <value>SIM_DIR</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.FLASH_INSTALL_DIR</name>
+ <value>APP_DIR</value>
+ </assignment>
+ <parameter name="autoSelectASMIAtom">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamilyString">
+ <type>java.lang.String</type>
+ <value>Cyclone III</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useASMIAtom">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <port>
+ <name>reset_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ <interface name="epcs_control_port" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isNonVolatileStorage</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isFlash</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>1</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>2048</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>address</name>
+ <direction>Input</direction>
+ <width>9</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect</role>
+ </port>
+ <port>
+ <name>dataavailable</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>dataavailable</role>
+ </port>
+ <port>
+ <name>endofpacket</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>endofpacket</role>
+ </port>
+ <port>
+ <name>read_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>read_n</role>
+ </port>
+ <port>
+ <name>readdata</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>readyfordata</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>readyfordata</role>
+ </port>
+ <port>
+ <name>write_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write_n</role>
+ </port>
+ <port>
+ <name>writedata</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ </interface>
+ <interface name="irq" kind="interrupt_sender" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedAddressablePoint">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>epcs_flash_controller_0.epcs_control_port</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="irqScheme">
+ <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <port>
+ <name>irq</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>irq</role>
+ </port>
+ </interface>
+ <interface name="external" kind="conduit" version="7.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>dclk</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>sce</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>sdo</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>data0</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ </interface>
+ </module>
+ <module name="timer_0" kind="altera_avalon_timer" version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.ALWAYS_RUN</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.FIXED_PERIOD</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SNAPSHOT</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PERIOD</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PERIOD_UNITS</name>
+ <value>"ms"</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.RESET_OUTPUT</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.FREQ</name>
+ <value>50000000u</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.LOAD_VALUE</name>
+ <value>49999ULL</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.COUNTER_SIZE</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.MULT</name>
+ <value>0.0010</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TICKS_PER_SEC</name>
+ <value>1000u</value>
+ </assignment>
+ <parameter name="alwaysRun">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="counterSize">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="fixedPeriod">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="period">
+ <type>java.lang.String</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="periodUnits">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.AlteraAvalonTimer$TimerPeriodUnit</type>
+ <value>MSEC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="resetOutput">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="snapshot">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="systemFrequency">
+ <type>long</type>
+ <value>50000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timeoutPulseOutput">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timerPreset">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.TimerPresets</type>
+ <value>CUSTOM</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>java.lang.Long</type>
+ <value>50000000</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>java.lang.Boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <port>
+ <name>reset_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ <interface name="s1" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isTimerDevice</name>
+ <value>1</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>NATIVE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>8</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>address</name>
+ <direction>Input</direction>
+ <width>3</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>writedata</name>
+ <direction>Input</direction>
+ <width>16</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>readdata</name>
+ <direction>Output</direction>
+ <width>16</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect</role>
+ </port>
+ <port>
+ <name>write_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write_n</role>
+ </port>
+ </interface>
+ <interface name="irq" kind="interrupt_sender" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedAddressablePoint">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>timer_0.s1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="irqScheme">
+ <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <port>
+ <name>irq</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>irq</role>
+ </port>
+ </interface>
+ </module>
+ <module name="uart_0" kind="altera_avalon_uart" version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.BAUD</name>
+ <value>115200</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.DATA_BITS</name>
+ <value>8</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.FIXED_BAUD</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PARITY</name>
+ <value>'N'</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.STOP_BITS</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SYNC_REG_DEPTH</name>
+ <value>2</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.USE_CTS_RTS</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.USE_EOP_REGISTER</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SIM_TRUE_BAUD</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SIM_CHAR_STREAM</name>
+ <value>""</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.FREQ</name>
+ <value>50000000u</value>
+ </assignment>
+ <parameter name="baud">
+ <type>int</type>
+ <value>115200</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baudError">
+ <type>double</type>
+ <value>0.01</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>50000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dataBits">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="fixedBaud">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="parity">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonUART.AlteraAvalonUART$UartParity</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="simCharStream">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="simInteractiveInputEnable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="simInteractiveOutputEnable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="simTrueBaud">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="stopBits">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="syncRegDepth">
+ <type>int</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useCtsRts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useEopRegister">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useRelativePathForSimFile">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>java.lang.Long</type>
+ <value>50000000</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>java.lang.Boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <port>
+ <name>reset_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ <interface name="s1" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isPrintableDevice</name>
+ <value>1</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>NATIVE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>8</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>address</name>
+ <direction>Input</direction>
+ <width>3</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>begintransfer</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>begintransfer</role>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect</role>
+ </port>
+ <port>
+ <name>read_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>read_n</role>
+ </port>
+ <port>
+ <name>write_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write_n</role>
+ </port>
+ <port>
+ <name>writedata</name>
+ <direction>Input</direction>
+ <width>16</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>readdata</name>
+ <direction>Output</direction>
+ <width>16</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>dataavailable</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>dataavailable</role>
+ </port>
+ <port>
+ <name>readyfordata</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>readyfordata</role>
+ </port>
+ </interface>
+ <interface name="external_connection" kind="conduit" version="7.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rxd</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ <port>
+ <name>txd</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ </interface>
+ <interface name="irq" kind="interrupt_sender" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedAddressablePoint">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>uart_0.s1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="irqScheme">
+ <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <port>
+ <name>irq</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>irq</role>
+ </port>
+ </interface>
+ </module>
+ <module name="jtag_uart_0" kind="altera_avalon_jtag_uart" version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.WRITE_DEPTH</name>
+ <value>64</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.READ_DEPTH</name>
+ <value>64</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.WRITE_THRESHOLD</name>
+ <value>8</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.READ_THRESHOLD</name>
+ <value>8</value>
+ </assignment>
+ <parameter name="allowMultipleConnections">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hubInstanceID">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readBufferDepth">
+ <type>int</type>
+ <value>64</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readIRQThreshold">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="simInputCharacterStream">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="simInteractiveOptions">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonJtagUART.AlteraAvalonJtagUART$JtagSimulationOptions</type>
+ <value>INTERACTIVE_ASCII_OUTPUT</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useRegistersForReadBuffer">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useRegistersForWriteBuffer">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useRelativePathForSimFile">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeBufferDepth">
+ <type>int</type>
+ <value>64</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeIRQThreshold">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <port>
+ <name>rst_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ <interface name="avalon_jtag_slave" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isPrintableDevice</name>
+ <value>1</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>NATIVE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>2</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>av_chipselect</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect</role>
+ </port>
+ <port>
+ <name>av_address</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>av_read_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>read_n</role>
+ </port>
+ <port>
+ <name>av_readdata</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>av_write_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write_n</role>
+ </port>
+ <port>
+ <name>av_writedata</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>av_waitrequest</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>waitrequest</role>
+ </port>
+ <port>
+ <name>dataavailable</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>dataavailable</role>
+ </port>
+ <port>
+ <name>readyfordata</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>readyfordata</role>
+ </port>
+ </interface>
+ <interface name="irq" kind="interrupt_sender" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedAddressablePoint">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value>jtag_uart_0.avalon_jtag_slave</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="irqScheme">
+ <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <port>
+ <name>av_irq</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>irq</role>
+ </port>
+ </interface>
+ </module>
+ <module
+ name="onchip_memory2_0"
+ kind="altera_avalon_onchip_memory2"
+ version="9.1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
+ <value>"onchip_memory2_0"</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
+ <value>"Automatic"</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.WRITABLE</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.DUAL_PORT</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SIZE_VALUE</name>
+ <value>1024u</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.CONTENTS_INFO</name>
+ <value>""</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
+ <value>"Auto"</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.INSTANCE_ID</name>
+ <value>"NONE"</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
+ <value>"DONT_CARE"</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+ <value>QPF_DIR</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+ <value>SIM_DIR</value>
+ </assignment>
+ <parameter name="allowInSystemMemoryContentEditor">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="blockType">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$BlockType</type>
+ <value>AUTO</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dataWidth">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>Cyclone III</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dualPort">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="initMemContent">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="initializationFileName">
+ <type>java.lang.String</type>
+ <value>onchip_memory2_0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="instanceID">
+ <type>java.lang.String</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="memorySize">
+ <type>long</type>
+ <value>1024</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readDuringWriteMode">
+ <type>com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$ReadDuringWriteMode</type>
+ <value>DONT_CARE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="simAllowMRAMContentsFile">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="slave1Latency">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="slave2Latency">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useNonDefaultInitFile">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useShallowMemBlocks">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writable">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk1" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="s1" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isNonVolatileStorage</name>
+ <value>0</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>1024</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>1024</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>address</name>
+ <direction>Input</direction>
+ <width>8</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect</role>
+ </port>
+ <port>
+ <name>clken</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clken</role>
+ </port>
+ <port>
+ <name>readdata</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>write</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write</role>
+ </port>
+ <port>
+ <name>writedata</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>byteenable</name>
+ <direction>Input</direction>
+ <width>4</width>
+ <role>byteenable</role>
+ </port>
+ </interface>
+ <interface name="clk2" kind="clock_sink" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk2</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="s2" kind="avalon_slave" version="9.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isNonVolatileStorage</name>
+ <value>0</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>long</type>
+ <value>1024</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>clk2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>long</type>
+ <value>1024</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>address2</name>
+ <direction>Input</direction>
+ <width>8</width>
+ <role>address</role>
+ </port>
+ <port>
+ <name>chipselect2</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>chipselect</role>
+ </port>
+ <port>
+ <name>clken2</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clken</role>
+ </port>
+ <port>
+ <name>readdata2</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>write2</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write</role>
+ </port>
+ <port>
+ <name>writedata2</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>byteenable2</name>
+ <direction>Input</direction>
+ <width>4</width>
+ <role>byteenable</role>
+ </port>
+ </interface>
+ </module>
+ <connection
+ name="clk_0.clk/cpu_0.clk"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="cpu_0.clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>cpu_0</endModule>
+ <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.instruction_master/cpu_0.jtag_debug_module"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x02801000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>instruction_master</startConnectionPoint>
+ <endModule>cpu_0</endModule>
+ <endConnectionPoint>jtag_debug_module</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.data_master/cpu_0.jtag_debug_module"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x02801000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>data_master</startConnectionPoint>
+ <endModule>cpu_0</endModule>
+ <endConnectionPoint>jtag_debug_module</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/sdram_0.clk"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="sdram_0.clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>sdram_0</endModule>
+ <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.instruction_master/sdram_0.s1"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.instruction_master"
+ end="sdram_0.s1">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x01000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>instruction_master</startConnectionPoint>
+ <endModule>sdram_0</endModule>
+ <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.data_master/sdram_0.s1"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="sdram_0.s1">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x01000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>data_master</startConnectionPoint>
+ <endModule>sdram_0</endModule>
+ <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/tri_state_bridge_0.clk"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="tri_state_bridge_0.clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>tri_state_bridge_0</endModule>
+ <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.instruction_master/tri_state_bridge_0.avalon_slave"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.instruction_master"
+ end="tri_state_bridge_0.avalon_slave">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x0000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>instruction_master</startConnectionPoint>
+ <endModule>tri_state_bridge_0</endModule>
+ <endConnectionPoint>avalon_slave</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.data_master/tri_state_bridge_0.avalon_slave"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="tri_state_bridge_0.avalon_slave">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x0000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>data_master</startConnectionPoint>
+ <endModule>tri_state_bridge_0</endModule>
+ <endConnectionPoint>avalon_slave</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/cfi_flash_0.clk"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="cfi_flash_0.clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>cfi_flash_0</endModule>
+ <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="tri_state_bridge_0.tristate_master/cfi_flash_0.s1"
+ kind="avalon_tristate"
+ version="9.1"
+ start="tri_state_bridge_0.tristate_master"
+ end="cfi_flash_0.s1">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x02400000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>tri_state_bridge_0</startModule>
+ <startConnectionPoint>tristate_master</startConnectionPoint>
+ <endModule>cfi_flash_0</endModule>
+ <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/epcs_flash_controller_0.clk"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="epcs_flash_controller_0.clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>epcs_flash_controller_0</endModule>
+ <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.instruction_master/epcs_flash_controller_0.epcs_control_port"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.instruction_master"
+ end="epcs_flash_controller_0.epcs_control_port">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x02801800</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>instruction_master</startConnectionPoint>
+ <endModule>epcs_flash_controller_0</endModule>
+ <endConnectionPoint>epcs_control_port</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.data_master/epcs_flash_controller_0.epcs_control_port"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="epcs_flash_controller_0.epcs_control_port">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x02801800</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>data_master</startConnectionPoint>
+ <endModule>epcs_flash_controller_0</endModule>
+ <endConnectionPoint>epcs_control_port</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.d_irq/epcs_flash_controller_0.irq"
+ kind="interrupt"
+ version="9.1"
+ start="cpu_0.d_irq"
+ end="epcs_flash_controller_0.irq">
+ <parameter name="irqNumber">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>d_irq</startConnectionPoint>
+ <endModule>epcs_flash_controller_0</endModule>
+ <endConnectionPoint>irq</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/timer_0.clk"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="timer_0.clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>timer_0</endModule>
+ <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.data_master/timer_0.s1"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x02802000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>data_master</startConnectionPoint>
+ <endModule>timer_0</endModule>
+ <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.d_irq/timer_0.irq"
+ kind="interrupt"
+ version="9.1"
+ start="cpu_0.d_irq"
+ end="timer_0.irq">
+ <parameter name="irqNumber">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>d_irq</startConnectionPoint>
+ <endModule>timer_0</endModule>
+ <endConnectionPoint>irq</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/uart_0.clk"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="uart_0.clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>uart_0</endModule>
+ <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.data_master/uart_0.s1"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="uart_0.s1">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x02802020</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>data_master</startConnectionPoint>
+ <endModule>uart_0</endModule>
+ <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.d_irq/uart_0.irq"
+ kind="interrupt"
+ version="9.1"
+ start="cpu_0.d_irq"
+ end="uart_0.irq">
+ <parameter name="irqNumber">
+ <type>int</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>d_irq</startConnectionPoint>
+ <endModule>uart_0</endModule>
+ <endConnectionPoint>irq</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/jtag_uart_0.clk"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="jtag_uart_0.clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>jtag_uart_0</endModule>
+ <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.data_master/jtag_uart_0.avalon_jtag_slave"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x02802040</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>data_master</startConnectionPoint>
+ <endModule>jtag_uart_0</endModule>
+ <endConnectionPoint>avalon_jtag_slave</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.d_irq/jtag_uart_0.irq"
+ kind="interrupt"
+ version="9.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber">
+ <type>int</type>
+ <value>3</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>d_irq</startConnectionPoint>
+ <endModule>jtag_uart_0</endModule>
+ <endConnectionPoint>irq</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/onchip_memory2_0.clk1"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk1">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>onchip_memory2_0</endModule>
+ <endConnectionPoint>clk1</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/onchip_memory2_0.clk2"
+ kind="clock"
+ version="9.1"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk2">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>onchip_memory2_0</endModule>
+ <endConnectionPoint>clk2</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.tightly_coupled_instruction_master_0/onchip_memory2_0.s1"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.tightly_coupled_instruction_master_0"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x1000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>tightly_coupled_instruction_master_0</startConnectionPoint>
+ <endModule>onchip_memory2_0</endModule>
+ <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+ name="cpu_0.tightly_coupled_data_master_0/onchip_memory2_0.s2"
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.tightly_coupled_data_master_0"
+ end="onchip_memory2_0.s2">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>long</type>
+ <value>0x0000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>cpu_0</startModule>
+ <startConnectionPoint>tightly_coupled_data_master_0</startConnectionPoint>
+ <endModule>onchip_memory2_0</endModule>
+ <endConnectionPoint>s2</endConnectionPoint>
+ </connection>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_avalon_new_sdram_controller</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>SDRAM Controller</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_avalon_cfi_flash</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>Flash Memory Interface (CFI)</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>nios_custom_instruction_master</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Custom Instruction Master</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>4</instanceCount>
+ <name>interrupt_sender</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Interrupt Sender</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>4</instanceCount>
+ <name>interrupt</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IConnection</subtype>
+ <displayName>Interrupt Connection</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>10</instanceCount>
+ <name>clock</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IConnection</subtype>
+ <displayName>Clock Connection</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>11</instanceCount>
+ <name>clock_sink</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Clock Input</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_avalon_timer</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>Interval Timer</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_avalon_tri_state_bridge</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>Avalon-MM Tristate Bridge</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>avalon_tristate</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IConnection</subtype>
+ <displayName>Avalon Memory Mapped Tristate Connection</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>avalon_tristate_slave</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Avalon Memory Mapped Tristate Slave</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>4</instanceCount>
+ <name>avalon_master</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Avalon Memory Mapped Master</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>9</instanceCount>
+ <name>avalon_slave</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Avalon Memory Mapped Slave</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>interrupt_receiver</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Interrupt Receiver</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_nios2</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>Nios II Processor</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>clock_source</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>Clock Source</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>clock_source</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Clock Output</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_avalon_onchip_memory2</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>On-Chip Memory (RAM or ROM)</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_avalon_uart</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>UART (RS-232 Serial Port)</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_avalon_epcs_flash_controller</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>EPCS Serial Flash Controller</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>avalon_tristate_master</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Avalon Memory Mapped Tristate Master</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_avalon_jtag_uart</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>JTAG UART</displayName>
+ <version>9.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>13</instanceCount>
+ <name>avalon</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IConnection</subtype>
+ <displayName>Avalon Memory Mapped Connection</displayName>
+ <version>6.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>3</instanceCount>
+ <name>conduit</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Conduit Endpoint</displayName>
+ <version>7.1</version>
+ </plugin>
+ <reportVersion>9.1 222</reportVersion>
+ <uniqueIdentifier>0023AE674DE00000012786918231</uniqueIdentifier>
+</EnsembleReport>
diff --git a/quartus/dionysos_sinet.qsf b/quartus/dionysos_sinet.qsf
new file mode 100644
index 0000000..0a82daa
--- /dev/null
+++ b/quartus/dionysos_sinet.qsf
@@ -0,0 +1,639 @@
+set_global_assignment -name TOP_LEVEL_ENTITY dionysos_top
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# sinet_su_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+# Set preflow scripts
+# ===================
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:dionysos_version_number.tcl"
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name LAST_QUARTUS_VERSION 8.0
+set_global_assignment -name INCREMENTAL_COMPILATION OFF
+
+
+
+# Clock inputs
+# --------------
+set_location_assignment PIN_G2 -to clock_50_i
+set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i
+set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i
+set_location_assignment PIN_G21 -to usb_clk_i
+set_location_assignment PIN_G22 -to sdfe_clk_20mhz_i
+set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i
+set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i
+set_location_assignment PIN_A12 -to aux_clk_n_i
+set_location_assignment PIN_B12 -to aux_clk_p_i
+set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i
+set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i
+set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i
+set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i
+
+# FPGA programming pins
+# ---------------------
+set_location_assignment PIN_E2 -to config_ce_n_o
+set_location_assignment PIN_D1 -to config_asd0_o
+set_location_assignment PIN_K1 -to config_data0_i
+set_location_assignment PIN_K2 -to config_dclk_o
+
+# FPGA bank 1
+# -------------
+set_location_assignment PIN_G4 -to nios_uart_txd_o
+set_location_assignment PIN_B2 -to nios_uart_rxd_i
+set_location_assignment PIN_G3 -to mstt_uart_txd_o
+set_location_assignment PIN_B1 -to mstt_uart_rxd_i
+set_location_assignment PIN_G5 -to gen_led_r_o[5]
+set_location_assignment PIN_E4 -to gen_led_g_o[5]
+set_location_assignment PIN_E3 -to iom_du_o
+set_location_assignment PIN_C2 -to iom_dd_i
+set_location_assignment PIN_C1 -to iom_fsc_o
+set_location_assignment PIN_D2 -to iom_dclk_o
+set_location_assignment PIN_H7 -to reserve0_i
+set_location_assignment PIN_J6 -to reserve1_i
+set_location_assignment PIN_E1 -to i2c_sda_io
+set_location_assignment PIN_F2 -to i2c_scl_o
+set_location_assignment PIN_F1 -to gen_led_r_o[4]
+set_location_assignment PIN_H8 -to gen_led_g_o[4]
+set_location_assignment PIN_J5 -to switch_i[0]
+set_location_assignment PIN_H5 -to switch_i[1]
+set_location_assignment PIN_L8 -to switch_i[2]
+set_location_assignment PIN_K8 -to switch_i[3]
+set_location_assignment PIN_K7 -to gen_led_r_o[0]
+set_location_assignment PIN_J4 -to gen_led_g_o[0]
+set_location_assignment PIN_H2 -to gp_led_o[0]
+set_location_assignment PIN_H1 -to gp_led_o[1]
+set_location_assignment PIN_J3 -to gp_led_o[2]
+set_location_assignment PIN_J2 -to gp_led_o[3]
+
+# FPGA bank 2
+# -------------
+set_location_assignment PIN_L6 -to ssram_d_io[2]
+set_location_assignment PIN_M6 -to ssram_a_o[17]
+set_location_assignment PIN_M2 -to ssram_bwc_n_o
+set_location_assignment PIN_M1 -to ssram_bwb_n_o
+set_location_assignment PIN_M4 -to ssram_ce_n_o
+set_location_assignment PIN_M3 -to ssram_bwd_n_o
+set_location_assignment PIN_N2 -to ssram_a_o[14]
+set_location_assignment PIN_N1 -to ssram_a_o[13]
+set_location_assignment PIN_L7 -to ssram_d_io[3]
+set_location_assignment PIN_M5 -to ssram_a_o[16]
+set_location_assignment PIN_P2 -to ssram_d_io[12]
+set_location_assignment PIN_P1 -to ssram_d_io[11]
+set_location_assignment PIN_R2 -to ssram_a_o[12]
+set_location_assignment PIN_R1 -to ssram_a_o[11]
+set_location_assignment PIN_N5 -to ssram_a_o[15]
+set_location_assignment PIN_P4 -to ssram_d_io[14]
+set_location_assignment PIN_P3 -to ssram_d_io[13]
+set_location_assignment PIN_U2 -to ssram_a_o[6]
+set_location_assignment PIN_U1 -to ssram_a_o[0]
+set_location_assignment PIN_V2 -to ssram_a_o[4]
+set_location_assignment PIN_V1 -to ssram_a_o[3]
+set_location_assignment PIN_P5 -to ssram_d_io[15]
+set_location_assignment PIN_N6 -to ssram_oe_n_o
+set_location_assignment PIN_M7 -to ssram_d_io[0]
+set_location_assignment PIN_M8 -to ssram_d_io[1]
+set_location_assignment PIN_N8 -to ssram_bwa_n_o
+set_location_assignment PIN_W2 -to ssram_a_o[2]
+set_location_assignment PIN_W1 -to ssram_d_io[16]
+set_location_assignment PIN_Y2 -to ssram_d_io[7]
+set_location_assignment PIN_Y1 -to ssram_d_io[6]
+set_location_assignment PIN_T3 -to ssram_a_o[7]
+set_location_assignment PIN_N7 -to ssram_we_n_o
+set_location_assignment PIN_P7 -to ssram_a_o[18]
+set_location_assignment PIN_AA2 -to ssram_d_io[5]
+set_location_assignment PIN_AA1 -to ssram_d_io[4]
+set_location_assignment PIN_V4 -to ssram_a_o[1]
+set_location_assignment PIN_V3 -to ssram_a_o[5]
+set_location_assignment PIN_P6 -to ssram_d_io[17]
+set_location_assignment PIN_T5 -to ssram_a_o[9]
+set_location_assignment PIN_T4 -to ssram_a_o[8]
+set_location_assignment PIN_R5 -to ssram_d_io[8]
+set_location_assignment PIN_R6 -to ssram_d_io[9]
+set_location_assignment PIN_R7 -to ssram_d_io[10]
+set_location_assignment PIN_T7 -to ssram_a_o[10]
+
+# FPGA bank 3
+# -------------
+set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i
+set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i
+set_location_assignment PIN_U8 -to et_phy1_crs_1_i
+set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0]
+set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1]
+set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2]
+set_location_assignment PIN_AA3 -to ssram_clk_o
+set_location_assignment PIN_AB3 -to reserve7_i
+set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3]
+set_location_assignment PIN_V7 -to et_phy1_col_1_i
+set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o
+set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0]
+set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1]
+set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2]
+set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3]
+set_location_assignment PIN_W7 -to et_phy1_int_1_i
+set_location_assignment PIN_Y7 -to reserve2_i
+set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i
+set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i
+set_location_assignment PIN_W8 -to et_phy1_crs_2_i
+set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0]
+set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1]
+set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2]
+set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3]
+set_location_assignment PIN_T11 -to et_phy1_col_2_i
+set_location_assignment PIN_V9 -to reserve3_i
+set_location_assignment PIN_V10 -to et_phy1_tx_en_2_o
+set_location_assignment PIN_U10 -to et_phy1_txd_2_o[0]
+set_location_assignment PIN_AA8 -to et_phy1_txd_2_o[1]
+set_location_assignment PIN_AB8 -to et_phy1_txd_2_o[2]
+set_location_assignment PIN_AA9 -to et_phy1_txd_2_o[3]
+set_location_assignment PIN_AB9 -to et_phy1_int_2_i
+set_location_assignment PIN_U11 -to et_phy1_mdc_o
+set_location_assignment PIN_V11 -to et_phy1_mdio_io
+set_location_assignment PIN_W10 -to rst_et_phy1_n_o
+set_location_assignment PIN_Y10 -to gen_led_r_o[3]
+set_location_assignment PIN_AA10 -to gen_led_g_o[3]
+
+# FPGA bank 4
+# -------------
+set_location_assignment PIN_AA13 -to otg_d_io[0]
+set_location_assignment PIN_AB13 -to otg_d_io[1]
+set_location_assignment PIN_AA14 -to otg_d_io[2]
+set_location_assignment PIN_AB14 -to otg_d_io[3]
+set_location_assignment PIN_V12 -to otg_d_io[4]
+set_location_assignment PIN_W13 -to otg_d_io[5]
+set_location_assignment PIN_Y13 -to otg_d_io[6]
+set_location_assignment PIN_AA15 -to otg_d_io[7]
+set_location_assignment PIN_AB15 -to otg_d_io[8]
+set_location_assignment PIN_U12 -to otg_d_io[9]
+set_location_assignment PIN_AA16 -to otg_d_io[10]
+set_location_assignment PIN_AB16 -to otg_d_io[11]
+set_location_assignment PIN_T12 -to otg_d_io[12]
+set_location_assignment PIN_T13 -to otg_d_io[13]
+set_location_assignment PIN_V13 -to otg_d_io[14]
+set_location_assignment PIN_W14 -to otg_d_io[15]
+set_location_assignment PIN_U13 -to otg_a_o[0]
+set_location_assignment PIN_V14 -to otg_a_o[1]
+set_location_assignment PIN_U14 -to otg_cs_n_o
+set_location_assignment PIN_U15 -to otg_we_n_o
+set_location_assignment PIN_V15 -to otg_oe_n_o
+set_location_assignment PIN_W15 -to otg_int0_i
+set_location_assignment PIN_T14 -to otg_int1_i
+set_location_assignment PIN_T15 -to otg_reset_n_o
+set_location_assignment PIN_AB18 -to otg_dreq0_i
+set_location_assignment PIN_AA17 -to otg_dreq1_i
+set_location_assignment PIN_AB17 -to otg_dack0_n_o
+set_location_assignment PIN_AA18 -to otg_dack1_n_o
+set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i
+set_location_assignment PIN_W17 -to gen_led_r_o[6]
+set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o
+set_location_assignment PIN_AB20 -to gen_led_r_o[2]
+set_location_assignment PIN_V16 -to gen_led_g_o[2]
+set_location_assignment PIN_U16 -to reserve4_i
+set_location_assignment PIN_U17 -to reserve5_i
+set_location_assignment PIN_T16 -to aux_clk_p_o
+set_location_assignment PIN_R16 -to aux_clk_n_o
+set_location_assignment PIN_R15 -to gen_led_g_o[6]
+
+# FPGA bank 5
+# -------------
+set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3]
+set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2]
+set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1]
+set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0]
+set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3]
+set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2]
+set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1]
+set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0]
+set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3]
+set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2]
+set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1]
+set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0]
+set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3]
+set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2]
+set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1]
+set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0]
+set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i
+set_location_assignment PIN_V21 -to et_phy2_crs_2_i
+set_location_assignment PIN_R20 -to rst_et_phy2_n_o
+set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i
+set_location_assignment PIN_U21 -to et_phy2_col_2_i
+set_location_assignment PIN_R18 -to et_phy2_crs_1_i
+set_location_assignment PIN_R19 -to et_phy2_col_1_i
+set_location_assignment PIN_N16 -to mpd_io[0]
+set_location_assignment PIN_R22 -to mpd_io[1]
+set_location_assignment PIN_R21 -to mpd_io[2]
+set_location_assignment PIN_P20 -to mpd_io[3]
+set_location_assignment PIN_P22 -to mpd_io[4]
+set_location_assignment PIN_P21 -to mpd_io[5]
+set_location_assignment PIN_N20 -to mpd_io[6]
+set_location_assignment PIN_N19 -to mpd_io[7]
+set_location_assignment PIN_N18 -to reserve6_i
+set_location_assignment PIN_N21 -to fpga_reset_n_i
+set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i
+set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o
+set_location_assignment PIN_AA20 -to et_phy2_int_1_i
+set_location_assignment PIN_M20 -to et_phy2_int_2_i
+set_location_assignment PIN_M19 -to et_phy2_mdc_o
+set_location_assignment PIN_M16 -to et_phy2_mdio_io
+set_global_assignment -name DEVICE EP3C40F484C6
+
+# FPGA bank 6
+# -------------
+set_location_assignment PIN_L22 -to flash_a_o[2]
+set_location_assignment PIN_L21 -to flash_a_o[4]
+set_location_assignment PIN_K19 -to fash_acc_o
+set_location_assignment PIN_K22 -to flash_a_o[6]
+set_location_assignment PIN_K21 -to flash_a_o[18]
+set_location_assignment PIN_J22 -to flash_a_o[12]
+set_location_assignment PIN_J21 -to flash_a_o[14]
+set_location_assignment PIN_H22 -to flash_a_o[13]
+set_location_assignment PIN_H21 -to flash_a_o[11]
+set_location_assignment PIN_K17 -to flash_a_o[9]
+set_location_assignment PIN_K18 -to flash_we_n_o
+set_location_assignment PIN_J18 -to flash_a_o[16]
+set_location_assignment PIN_F22 -to flash_oe_n_o
+set_location_assignment PIN_F21 -to flash_d_io[1]
+set_location_assignment PIN_H20 -to flash_a_o[8]
+set_location_assignment PIN_H19 -to flash_reset_n_o
+set_location_assignment PIN_E22 -to flash_a_o[10]
+set_location_assignment PIN_E21 -to flash_a_o[20]
+set_location_assignment PIN_H18 -to flash_a_o[7]
+set_location_assignment PIN_J17 -to flash_a_o[15]
+set_location_assignment PIN_H16 -to flash_a_o[3]
+set_location_assignment PIN_D22 -to flash_a_o[17]
+set_location_assignment PIN_D21 -to flash_a_o[19]
+set_location_assignment PIN_F20 -to flash_d_io[3]
+set_location_assignment PIN_F19 -to flash_d_io[4]
+set_location_assignment PIN_G18 -to flash_a_o[1]
+set_location_assignment PIN_H17 -to flash_a_o[5]
+set_location_assignment PIN_C22 -to flash_d_io[5]
+set_location_assignment PIN_C21 -to flash_a_o[21]
+set_location_assignment PIN_B22 -to flash_d_io[0]
+set_location_assignment PIN_B21 -to flash_a_o[0]
+set_location_assignment PIN_C20 -to flash_d_io[2]
+set_location_assignment PIN_D20 -to flash_d_io[7]
+set_location_assignment PIN_F17 -to flash_d_io[6]
+set_location_assignment PIN_G17 -to flash_ce_n_o
+
+# FPGA bank 7
+# -------------
+set_location_assignment PIN_F16 -to dram_a_o[0]
+set_location_assignment PIN_E16 -to dram_a_o[1]
+set_location_assignment PIN_F15 -to dram_a_o[2]
+set_location_assignment PIN_G16 -to dram_a_o[3]
+set_location_assignment PIN_G15 -to dram_a_o[4]
+set_location_assignment PIN_F14 -to dram_a_o[5]
+set_location_assignment PIN_H15 -to dram_a_o[6]
+set_location_assignment PIN_H14 -to dram_a_o[7]
+set_location_assignment PIN_D17 -to dram_a_o[8]
+set_location_assignment PIN_C19 -to dram_a_o[9]
+set_location_assignment PIN_D19 -to dram_a_o[10]
+set_location_assignment PIN_A20 -to dram_a_o[11]
+set_location_assignment PIN_B20 -to dram_clk_o
+set_location_assignment PIN_C17 -to dram_d_io[0]
+set_location_assignment PIN_B19 -to dram_d_io[1]
+set_location_assignment PIN_A19 -to dram_d_io[2]
+set_location_assignment PIN_A18 -to dram_d_io[3]
+set_location_assignment PIN_B18 -to dram_d_io[4]
+set_location_assignment PIN_D15 -to dram_d_io[5]
+set_location_assignment PIN_E15 -to dram_d_io[6]
+set_location_assignment PIN_G14 -to dram_d_io[7]
+set_location_assignment PIN_G13 -to dram_d_io[8]
+set_location_assignment PIN_A17 -to dram_d_io[9]
+set_location_assignment PIN_B17 -to dram_d_io[10]
+set_location_assignment PIN_A16 -to dram_d_io[11]
+set_location_assignment PIN_B16 -to dram_d_io[12]
+set_location_assignment PIN_C15 -to dram_d_io[13]
+set_location_assignment PIN_E14 -to dram_d_io[14]
+set_location_assignment PIN_F13 -to dram_d_io[15]
+set_location_assignment PIN_B15 -to dram_cke_o
+set_location_assignment PIN_C13 -to dram_ldqm_o
+set_location_assignment PIN_D13 -to dram_udqm_o
+set_location_assignment PIN_E13 -to dram_we_n_o
+set_location_assignment PIN_A14 -to dram_cas_n_o
+set_location_assignment PIN_B14 -to dram_ras_n_o
+set_location_assignment PIN_A13 -to dram_cs_n_o
+set_location_assignment PIN_B13 -to dram_ba0_n_o
+set_location_assignment PIN_E12 -to dram_ba1_n_o
+set_location_assignment PIN_F11 -to dram_a_o[12]
+
+# FPGA bank 8
+# -------------
+set_location_assignment PIN_D10 -to sdfe_dout_0_i
+set_location_assignment PIN_E10 -to sdfe_din_0_o
+set_location_assignment PIN_A10 -to sdfe_aux_0_0_o
+set_location_assignment PIN_B10 -to sdfe_aux_0_1_o
+set_location_assignment PIN_A9 -to sdfe_aux_0_2_o
+set_location_assignment PIN_B9 -to sdfe_aux_0_3_i
+set_location_assignment PIN_C10 -to sdfe_aux_0_4_i
+set_location_assignment PIN_G11 -to sdfe_aux_0_5_i
+set_location_assignment PIN_A8 -to sdfe_refclk_0_i
+set_location_assignment PIN_B8 -to reserve8_i
+set_location_assignment PIN_B7 -to sdfe_dout_3_i
+set_location_assignment PIN_A6 -to sdfe_din_3_o
+set_location_assignment PIN_B6 -to sdfe_aux_3_0_o
+set_location_assignment PIN_E9 -to sdfe_aux_3_1_o
+set_location_assignment PIN_C8 -to sdfe_aux_3_2_o
+set_location_assignment PIN_C7 -to sdfe_aux_3_3_i
+set_location_assignment PIN_H11 -to sdfe_aux_3_4_i
+set_location_assignment PIN_H10 -to sdfe_aux_3_5_i
+set_location_assignment PIN_A5 -to sdfe_refclk_3_i
+set_location_assignment PIN_B5 -to gen_led_r_o[1]
+set_location_assignment PIN_G10 -to gen_led_g_o[1]
+set_location_assignment PIN_F10 -to sdfe_scdi_o
+set_location_assignment PIN_C6 -to sdfe_scdo_i
+set_location_assignment PIN_D7 -to sdfe_scck_o
+set_location_assignment PIN_A4 -to rst_sdfe_n_o
+set_location_assignment PIN_B4 -to mprdy_n_io
+set_location_assignment PIN_F8 -to mpcs_n_o
+set_location_assignment PIN_G8 -to mpwr_n_o
+set_location_assignment PIN_A3 -to mprd_n_o
+set_location_assignment PIN_B3 -to mpint_n_i
+set_location_assignment PIN_D6 -to mpclk_o
+set_location_assignment PIN_E7 -to isdn_cs_n_o
+set_location_assignment PIN_C3 -to mpad_o[0]
+set_location_assignment PIN_C4 -to mpad_o[1]
+set_location_assignment PIN_F7 -to mpad_o[2]
+set_location_assignment PIN_G7 -to mpad_o[3]
+set_location_assignment PIN_F9 -to mpad_o[4]
+set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o
+
+
+
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+
+# Assembler Assignments
+# =====================
+
+
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to mdio_io
+
+
+
+#SOURCES
+#-------
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to et_phy2_tx_clk_2_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_reset_n_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_sdfe_n_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_0_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_1_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_2_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_3_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_4_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_5_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_0_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_1_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_2_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_3_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_4_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_5_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_din_0_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_din_3_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_dout_0_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_dout_3_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_refclk_0_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_refclk_3_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scck_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scdi_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scdo_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reserve8_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpint_n_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mprd_n_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mprdy_n_io
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpwr_n_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to isdn_cs_n_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpclk_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpcs_n_o
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_r_o[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_g_o[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to et_phy_clk_50mhz_o
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[7]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[8]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[9]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[10]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[11]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[12]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[13]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[14]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[15]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[16]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[17]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 25 OHM WITHOUT CALIBRATION" -to ssram_clk_o
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE su_debug.stp
+set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name QIP_FILE ../../../lib/altera/sinet_pll.qip
+set_global_assignment -name VHDL_FILE ../../../lib/altera/sinet_pll.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/sinet_filter.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/prp_filter.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/learning_table/ip_request_to_learningtable.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/learning_table/address_comparator.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/arp_filter.vhd
+set_global_assignment -name VHDL_FILE descriptor_memory.vhd
+set_global_assignment -name VHDL_FILE sgdma_rx.vhd
+set_global_assignment -name VHDL_FILE sgdma_tx.vhd
+set_global_assignment -name VHDL_FILE ISP1362.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/rmii_phy_to_mii_mac.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su_ucom_generic_globals.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/edge_det.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/pwm_unit.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/led_controller.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/learning_table/sinet_types.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learning_table.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learningtable_mng.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learningtable_ram_mng.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_rx_mux.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/dp_ram_intern.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_core_top.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo_read_mng.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo_write_mng.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_filter.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_generic_globals.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/ucom/dsl_port_switch.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/ucom/ucom_generic_top.vhd
+set_global_assignment -name VHDL_FILE firmware_id_pkg.vhd
+set_global_assignment -name SDC_FILE dionysos_sinet.sdc
+set_global_assignment -name QIP_FILE nios_1.qip
+set_global_assignment -name VHDL_FILE ../../../lib/bus/avalon/dm9000a_if.vhd
+set_global_assignment -name VHDL_FILE nios_1_burst_3.vhd
+set_global_assignment -name VHDL_FILE nios_1_burst_1.vhd
+set_global_assignment -name VHDL_FILE nios_1_burst_2.vhd
+set_global_assignment -name VHDL_FILE nios_1_burst_0.vhd
+set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_sysclk.vhd -library work
+set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_tck.vhd -library work
+set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_wrapper.vhd -library work
+set_global_assignment -name VHDL_FILE cpu_0_mult_cell.vhd -library work
+set_global_assignment -name VHDL_FILE cpu_0_test_bench.vhd -library work
+set_global_assignment -name VHDL_FILE cpu_0.vhd -library work
+set_global_assignment -name VHDL_FILE epcs_controller.vhd -library work
+set_global_assignment -name VHDL_FILE nios_16bit_interface_wbd_1.vhd -library work
+set_global_assignment -name VHDL_FILE nios_1.vhd -library work
+set_global_assignment -name VHDL_FILE nios_interrupt_quirk_hdcl_rx.vhd -library work
+set_global_assignment -name VHDL_FILE nios_interrupt_quirk_hdlc_tx.vhd -library work
+set_global_assignment -name VHDL_FILE nios_interrupt_quirk_mac.vhd -library work
+set_global_assignment -name VHDL_FILE sdram_0_test_component.vhd -library work
+set_global_assignment -name VHDL_FILE sdram_0.vhd -library work
+set_global_assignment -name VHDL_FILE sysid.vhd -library work
+set_global_assignment -name VHDL_FILE timer_0.vhd -library work
+set_global_assignment -name VHDL_FILE timer_1.vhd -library work
+set_global_assignment -name VHDL_FILE uart_0.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/pck_crc16_d8.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/ribu.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx_crc.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx_buffer.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx_crc.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx_buffer.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/hdlc_avalon_if.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/phy_init_top.vhd -library hdlc
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/uart.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/ccitt_crc_generator.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/communication_register.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_read_dfe_to_su.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_read_su_to_dfe.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_write_dfe_to_su.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_write_su_to_dfe.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/ethernet_header_plus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/frame_analyzer.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/framerasen_generator.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/priority_mux.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/rahmen_minus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/rahmen_plus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/sequence_number_crc_generator.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/sicherungs_fsm.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/access_mux.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dfe_connector_top.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/misc/reduce_pkg.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/misc/ines_vhdl_lib_base_pkg.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/register_r.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/buf_sync.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/register_rw.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/bibuf_async.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/bibuf_sync.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/reset_sync.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/generic_sp_ram.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/misc/components/ram.vhd -library ines_misc
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/clock_logic.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/pkg_rt_nrt_segment.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_arbit.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_flag_det.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_ser_par.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_arbit.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_flag_data_mux.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_par_ser.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rt_nrt_segment_top.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/clk_edge_det.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_top.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_top.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/bus/wishbone/wb_register_rw.vhd -library ines_bus
+set_global_assignment -name VHDL_FILE ../../../lib/bus/avalon/avalon_multimaster_16.vhd -library ines_bus
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/ethernet_pkg.vhd -library ines_ethernet
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/prp_rct_detect.vhd -library ines_ethernet
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/crc_generator.vhd -library ines_ethernet
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/rmii_in_out.vhd -library ines_ethernet
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mii_management_transmit.vhd -library ines_ethernet
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mdio_interface.vhd -library ines_ethernet
+set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mac_filter.vhd -library ines_ethernet
+set_global_assignment -name VHDL_FILE ../../../lib/altera/hash_ram_112.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/altera/mac_table_96.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/arbiter_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/ram_arbiter_sram.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/ram_arbiter_ssram.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_core_register_mapping.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/traffic_led_delay.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/learn_stw_addr.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/counter_32.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/counters.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/cpu_interface.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_queue.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_fifo.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_fifo.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/hash_lookup.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/seq_count_ram.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/seq_counter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_serializer.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_filter_rules.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/mac_addr_comparator.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_mac_filter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_processing12.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_processing3.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_processing.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_core.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/region_global.vhd
+set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su/su_generic_top.vhd -library work
+set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su_ucom_generic_top.vhd -library work
+set_global_assignment -name VHDL_FILE ../dionysos_top.vhd
+set_global_assignment -name SIGNALTAP_FILE tx_serializer.stp
+set_global_assignment -name SIGNALTAP_FILE su_input_ports.stp
+set_global_assignment -name SIGNALTAP_FILE su_input_ports_neuer_su_core_und_neuer_hdlc_.stp
+set_global_assignment -name SIGNALTAP_FILE su_input_ports_lange_frames_und_wenig_segmente.stp
+set_global_assignment -name SIGNALTAP_FILE rmii_phy_to_mii_mac_debug.stp
+set_global_assignment -name SIGNALTAP_FILE rmii_phy_to_mii_mac_debug_2.stp
+set_global_assignment -name SIGNALTAP_FILE tse_mac_debug.stp
+set_global_assignment -name SIGNALTAP_FILE tsgdma_debug.stp
+set_global_assignment -name SIGNALTAP_FILE tse_mag_debug.stp
+set_global_assignment -name SIGNALTAP_FILE su_debug.stp
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-21 09:39:57 +0000